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dec, 2011 v0.13p f75113 f75113 low power gpio with led function release date: dec, 2011 version: v0.13p
dec, 2011 v0.13p f75113 f75113 datasheet revision history version date page revision history v0.10p 2010/12 preliminary version v0.11p 2011/01 4, 8 63-65 91-92 1. add serirq on F75113U pin5 2. add register 50 ~ 54h 3. update reference circuits v0.12p 2011/07 17, 21 30, 31 39, 40 48, 49 59, 60 74, 75 68 68 84 87 1. update global control register for lpc interface 2. update gpio0x input de-bounce register ? index 16h 3. update gpio1x input de-bounce register ? index 26h 4. update gpio2x input de-bounce register ? index 36h 5. update gpio3x input de-bounce register ? index 46h 6. update gpio4x input de-bounce register ? index 76h 7. add chip id1 & id 2 register ? index 5ah, 5bh 8. add vendor id1 & id2 register ? index 5dh, 5eh 9. delete 32 qfn package 10. update reference circuits (for spi) v0.13p 2011/12 1. made clarification and correction 2. modify pin 9~16 type please note that all data and specifications are subject to change without notice. a ll the trade marks of products and companie s mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances , devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers us ing or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for an y damages resulting from such improper use or sales.
dec,2011 v0.13p - 1 - f75113 table of contents 1. general des cription ........................................................................................................... ............................- 3 - 2. features ...................................................................................................................... ..........................................- 3 - 3. key specific ations ............................................................................................................ ................................- 4 - 4. block di agram ................................................................................................................. ...................................- 5 - 5. pin configuration ............................................................................................................................... ...............- 6 - 6. pin descri ption ............................................................................................................... ....................................- 7 - 6.1 power pin ..................................................................................................................... ............................... - 7 - 6.2 gpio func tion ................................................................................................................. ............................ - 7 - 6.3 access interface .............................................................................................................. ............................ - 9 - 7. functional description ........................................................................................................ ....................... - 10 - a ccess i nterface .............................................................................................................................. .................. - 10 - gpio f unction .............................................................................................................................. ...................... - 10 - led f unction .............................................................................................................................. ........................ - 13 - smi f unction .............................................................................................................................. ......................... - 13 - w atch d og t imer f unction .............................................................................................................................. ... - 13 - p ower -d own c ontrol f unction ........................................................................................................................ - 14 - 8. register d escription .......................................................................................................... .......................... - 16 - global control registers (for lpc interface) ....................................................................................................... - 16 - gpio control registers ........................................................................................................ ............................... - 17 - 9. electrical cha racteristic ..................................................................................................... ................... - 76 - a bsolute m aximum r atings .............................................................................................................................. .. - 76 - dc c haracteristics .............................................................................................................................. .............. - 76 - ac c haracteristics .............................................................................................................................. .............. - 77 - 9.3.1 lpc in terface ........................................................................................................... .................................. - 77 - 9.3.2 serialized irq interf ace ...................................................................................................... .............. - 79 - 10. ordering information .......................................................................................................... ..................... - 82 - 11. top marking spec ification ..................................................................................................... .................. - 82 - 12. package dime nsions ............................................................................................................ ....................... - 83 -
dec,2011 v0.13p - 2 - f75113 13. application circuits .......................................................................................................... ......................... - 85 -
dec,2011 v0.13p - 3 - f75113 1. general description f75113 is a low power general purpose io chip providing 40 gpio. level or pulse mode can be programmed by registers so all gpio can be progra mmed to logic one, zero, high pulse or low pulse. gpio0x~gpio2x can be programmed to be power led. f75113 includes two sets of watchdog timer for system reset. besides, two power-down modes (manual or smart) can be selected to save power and control the total consumption under 10ua, so f75113 c an fit the requirement of mobile device such as pda or cell phone. 2. features support up to 40 gpio pins each gpio pin can be programmed to be high/low level or pulse mode each gpio pin has de-bounce function support 8 gpio pins for low level(v ih > 0.9v, v il <0.3v) input mode 24 pins can be programmed to be led 8 pins has smi function two sets of watchdog timer two power down mode selection --- m anual or smart power management mode support lpc/smbus/spi interface package in 48-tqfp
dec,2011 v0.13p - 4 - f75113 3. key specifications supply voltage 3.0 v to 3.6v operating supply current testing condition: 1. enable smart power-down 2. access 1 register per 100 ms for each interface interface operation current (max.) lpc 2ma spi 100ua smbus 100ua power down current 10ua typ.
dec,2011 v0.13p - 5 - f75113 4. block diagram lpc / smbus / spi gpio controller smi controller led controller wdt controller pd controller host f75113 sirq controller control bus
dec,2011 v0.13p - 6 - f75113 5. pin configuration
dec,2011 v0.13p - 7 - f75113 6. pin description i/o 16st5v ttl level bi-directional pin with schmitt trigger, 16 ma source-sink capability and 5v tolerance i/ood 16st5v ttl level bi-directional pin with schmitt tri gger, can select to od or out by register, with 16 m a source-sink capability and 5v tolerance i/od 16st5v ttl level bi-directional pin with schmitt trigger, open-drain output with 16 ma sink capability, 5v tolerance o 16-5v output pin with 16 ma source-sink capabilit y , 5v tolerance. ood 16-5v od or out selected by register with 16 ma sink capability, 5v tolerance. in st , 5v ttl level input pin with schmitt trigger, 5v tolerance. in lv low level input pin a in input pin (analog) p power 6.1 power pin pin no. pin name type description 08 vdd p standard power supply voltage input with 3.3v 41 vss p gnd 6.2 gpio function pin no. pin name type pwr description 21,22, 23,24 gpio07, gpio06, gpio05, gpio04 i/ood 16st5v vdd general purpose i/o pins. led07, led06, led05, led04 ood 16-5v vdd power led. blink frequency selection and led function selected by register setting. rstout2 ood 16-5v vdd wdt2 resetout signal output. 25,26, 27,28 gpio03, gpio02 gpio01, gpio00 i/ood 16st5v vdd general purpose i/o pins. led03, led02, led01, led00 ood 16-5v vdd power led. blink frequency selection and led function selected by register setting. rstout1 ood 16-5v vdd wdt1 resetout signal output. 33,34, 35,36, 37,38, 39,40 gpio17, gpio16, gpio15, gpio14, i/ood 16st5v vdd general purpose i/o pins.
dec,2011 v0.13p - 8 - f75113 gpio13, gpio12, gpio11, gpio10 led17, led16, led15, led14, led13, led12, led11, led10 ood 16-5v vdd power led. blink frequency selection and led function selected by register setting. 09 gpio27, i/ood 16st,5v in lv vdd general purpose i/o pins. the gpio2x port support low level input signal by register 0x3fh setting. led27 ood 16-5v vdd power led. blink frequency selection and led function selected by register setting. 10,11, 12,13, 14,15, 16 gpio26, gpio25, gpio24, gpio23, gpio22, gpio21, gpio20 i/ood 16st,5v in lv vdd general purpose i/o pins. the gpio2x port support low level input signal by register 0x3fh setting. led26, led25, led24, led23, led22, led21, led20 ood 16-5v vdd power led. blink frequency selection and led function selected by register setting. 29,30, 31,32 gpio33, gpio32, gpio31, gpio30 i/ood 16st5v vdd general purpose i/o pins. 17,18, 19,20 gpio37, gpio36, gpio35, gpio34 i/ood 16st5v vdd general purpose i/o pins. 42,43, 44, 45 gpio43, gpio42, gpio41, gpio40 i/ood 16st5v vdd general purpose i/o pins. 06, 07 gpio45, gpio44 i/ood 16st5v vdd general purpose i/o pins.
dec,2011 v0.13p - 9 - f75113 6.3 access interface pin no. (F75113U) pin name type pwr description 46 lclk in st5v vdd lpc clock input. smbclk in st5v vdd smbus clock. spi_clk in st5v vdd spi clock. 47 lframe# in st5v vdd lpc lframe# signal. smbdat i/od 16st5v vdd smbus data spi_cs# in st5v vdd spi chip select 48 lreset# in st5v vdd lpc reset signal spi_mosi in st5v vdd spi master output, slave input 01 lad0 i/o 16st5v vdd lpc lad signal. spi_miso o 16-5v vdd spi master input, slave output 02,03 lad1, lad2 i/o 16st5v vdd lpc lad signal. 04 lad3 i/o 16st5v vdd lpc lad signal. gpio47 i/ood 16st5v vdd general purpose i/o pin. 05 serirq i/o 16st5v vdd serial irq input/output. (for lpc interface) gpio46 i/ood 16st5v vdd general purpose i/o pin.
dec,2011 v0.13p - 10 - f75113 7. functional description access interface the f75113 provides three auto-detected access interfaces , lpc, smbus or spi, to read/write internal registers. in lpc interface, the default address of configuration register i/o port is 2eh. when user writes data 10h to lpc configuration register 27h, the address of configuration register i/o port will be 4eh. in smbus interface, serial bus address default value is 6eh (0110_1110). another spi interface only care the least eight bits (lsb) of 24 bits address. spi interface write register by 02h inst ruction (page program) and read register by 03h instruction (read data). also spi interface supported byte write/read function. besides, the pin 46, 47, 48, 1, 2, 3, 4 are multi-functi on pins. if user want to access internal register by lpc interface, the f75113 will only supported 39 gpio function and the pin 4 won?t be used for gpio function. if user wants to access internal register by smbus interface, the pin 48, 1, 2, 3 must be set internal pull-high with 10k ? . when user don?t use the pin 4 (gpio function), the pin will must be set inte rnal pull-high. in spi interfac e, the pin 2, 3 must be set internal pull-high with 10k ? . also, the pin 4 will be selectively set internal pull-high with 10k ? by user. gpio function the f75113 with gpio0x~gpio4x general purpose i/o port is composed of independent i/o pins controlled and controls multi-pin function by index 02~06h register. each of gpio group has input capability, output (push-pull and open-drain) capability, internal pull-up resister with 10k ? . also f75113 has gpio2x groups with the low level input, led, smi and rstout function. please check below table how to select the gpio multi-function pin that user wants.
dec,2011 v0.13p - 11 - f75113 group pin function1 condition function2 condition function3 condition function4 condition pull cap gpio0 0 28 gpio00 gpio00_md=0 led00 gpio00_md=1 smi gpio00_md=2 rstout1 gpio00_md=3 up 1 27 gpio01 gpio01_md=0 led01 gpio01_md=1 smi gpio01_md=2 rstout1 gpio01_md=3 up 2 26 gpio02 gpio02_md=0 led02 gpio02_md=1 smi gpio02_md=2 rstout1 gpio02_md=3 up 3 25 gpio03 gpio03_md=0 led03 gpio03_md=1 smi gpio03_md=2 rstout1 gpio03_md=3 up 4 24 gpio04 gpio04_md=0 led04 gpio04_md=1 smi gpio04_md=2 rstout2 gpio04_md=3 up 5 23 gpio05 gpio05_md=0 led05 gpio05_md=1 smi gpio05_md=2 rstout2 gpio05_md=3 up 6 22 gpio06 gpio06_md=0 led06 gpio06_md=1 smi gpio06_md=2 rstout2 gpio06_md=3 up 7 21 gpio07 gpio07_md=0 led07 gpio07_md=1 smi gpio07_md=2 rstout2 gpio07_md=3 up gpio1 0 40 gpio10 gpio10_md=0 led10 gpio10_md=1 up 1 39 gpio11 gpio11_md=0 led11 gpio11_md=1 up 2 38 gpio12 gpio12_md=0 led12 gpio12_md=1 up 3 37 gpio13 gpio13_md=0 led13 gpio13_md=1 up 4 36 gpio14 gpio14_md=0 led14 gpio14_md=1 up 5 35 gpio15 gpio15_md=0 led15 gpio15_md=1 up 6 34 gpio16 gpio16_md=0 led16 gpio16_md=1 up 7 33 gpio17 gpio17_md=0 led17 gpio17_md=1 up gpio2 0 16 gpio20/lv_in gpio20_md=0 led20 gpio20_md=1 up 1 15 gpio21/lv_in gpio21_md=0 led21 gpio21_md=1 up 2 14 gpio22/lv_in gpio22_md=0 led22 gpio22_md=1 up 3 13 gpio23/lv_in gpio23_md=0 led23 gpio23_md=1 up 4 12 gpio24/lv_in gpio24_md=0 led24 gpio24_md=1 up 5 11 gpio25/lv_in gpio25_md=0 led25 gpio25_md=1 up 6 10 gpio26/lv_in gpio26_md=0 led26 gpio26_md=1 up 7 09 gpio27/lv_in gpio27_md=0 led27 gpio27_md=1 up gpio3 0 32 gpio30 up 1 31 gpio31 up 2 30 gpio32 up 3 29 gpio33 up 4 20 gpio34 up 5 19 gpio35 up 6 18 gpio36 up 7 17 gpio37 up gpio4 0 45 gpio40 up 1 44 gpio41 up 2 43 gpio42 up 3 42 gpio43 up 4 07 gpio44 up 5 06 gpio45 up 6 05 sirq/gpio46 cann?t use gpio46 under lpc interface up 7 04 gpio47 cann?t use gpio47 under lpc interface up
dec,2011 v0.13p - 12 - f75113 f75113 provides multi-function to system control by gpio0x_md, gpio1x_md or gpio2x_md setting. there is a figure describe how multi-function pin will be applied to f75113. gpio_md gpioindat vdd gpioup function1 10k ? function2 function3 function4 f75113 provides eight low level input pins at gpio2x por t. there is a figure describe how low level input will be designed. gpio2x_md gpio2xindat vdd gpio2xup gpio2x 10kohms led2x low level detect gpio2xlv_en
dec,2011 v0.13p - 13 - f75113 led function f75113 provides 24 pin led (gpio0x~gpio2x) display for system control. the led b linked by 0.25hz, 0.5hz, 1hz and 2hz with open drain capability (default). ther e is a figure describe how the leds will perform. 0.25hz 0.5hz 1hz 2hz 100msec 400msec (duty cycle = 97.5%) (duty cycle = 95%) (duty cycle = 90%) (duty cycle = 80%) smi function f75113 provides 7 smi output pins for system control. also, smi can be programming to level mode or pulse mode. in pulse mode, users can select 200us or 150ms pul se width for smi output. then, the smi can be triggered by any of the gpio0x ~ gpio4x pins. watchdog timer function f75113 provides two sets of watchdog timers for syst em reset. the watchdog timer1 timeout unit is set to second and range is 0 to 127 seconds. when the timeout has occurred, that will generate a active pulse signal or level signal. there is a figure describe how watchdog timer output rstout signal. count down to zero 500us count down to zero 100ms watchdog timer 1 0~127sec 0~127sec pulse width 500us pulse width 100ms rstout1 rstout1 the watchdog timer2 timeout unit is set to second or minutes and range is 0 to 255. when the timeout has occurred, that will generate a active pulse signal or level signal.
dec,2011 v0.13p - 14 - f75113 count down to zero 1ms count down to zero 20ms watchdog timer 2 0~255(sec or minute) pulse width 1ms pulse width 20ms count down to zero 100ms pulse width 100ms count down to zero 5s pulse width 5s 0~255(sec or minute) 0~255(sec or minute) 0~255(sec or minute) rstout2 rstout2 rstout2 rstout2 power-down control function f75113 provides smart power down and manual power down. in the smart power down mode, if all functions idle more then 10ms (default 63h), the chip would auto po wer down. also, it would wakeup when gpio state change or read/write the registers. there is a figure describe how f75113 auto-power-down the system. in manual power down, if users set bit 0 to one at i ndex 01h of configuration r egisters, the f75113 will be power down instantly. there is a figure describe how f75113 power-down the system in manual power down mode.
dec,2011 v0.13p - 15 - f75113 interface_wakeup led_busy smi_busy wdt_busy smart_pd_mode power down 10msec(default) (0~25.6msec) internal 500khz clock 10msec(default) (0~25.6msec) gpio_wakeup gpio_busy(pulse mode) smart power down timing figure gpio_wakeup smart_pd_mode power down manual_power_down manual power down timing figure set manual power down enable set manual power down enable below figure describes f75113 power-down design function. smart_power_down manual_power_down smart_pd_mode pd_timer auto_wakeup gp_wakeup gp_busy(pulse mode) wdt1_busy/wdt2_busy led0_busy/led1_busy/led2_busy smi_busy access_busy power down manual pd control 0 1 power down logic figure
dec,2011 v0.13p - 16 - f75113 8. register description when users access intern al registers by lpc interfac e, the configurati on register will be used to control the behavior of the corresponding devices. to configure the regi ster, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 2eh and 2fh respectively. write data 10h in index 27h of global control register to change the default value to 4eh/4fh. to enable configuration, the entry key 50h must be written to the index port. to dis able configuration, write exit key aah to the index port. following is an example to enable configurati on and disable configuration by using debug. -o 2e 50 -o 2e 50 (enable configuration) -o 2e aa (disable configuration) the following is a register map (total devices) grouped in hexa decimal address order, which shows a summary of all registers an d their default value. please refer each device chapt er if you want more detail information. global control registers (for lpc interface) ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 0 0 0 1 0 0 0 0 21 chip id register 0 0 0 1 0 0 0 1 23 vendor id register 0 0 0 1 1 0 0 1 24 vendor id register 0 0 1 1 0 1 0 0 27 configuration port select register - - - 0 - - - - 30 base address enable - - - - - - - 0 8.1.1 global ? logic device number register - index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: global control registers. 01h: select gpio control registers.
dec,2011 v0.13p - 17 - f75113 8.1.2 global ? chip id register - index 20h bit name r/w default description 7-0 chip_id1 r 10h chip id 1 of f75113. 8.1.3 global ? chip id register - index 21h bit name r/w default description 7-0 chip_id2 r 11h chip id 1 of f75113. 8.1.4 global ? vendor id register - index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1 of fintek devices. 8.1.5 global ? vendor id register - index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 8.1.5 global ? configuration port select register - index 27h bit name r/w default description 7-5 reserved - - reserved 4 cfg_port_sel r/w 0 configuration port select register. 3-0 reserved - - reserved 8.1.5 global ? base address enable register - index 30h bit name r/w default description 7-1 reserved - - reserved 0 baddr_en r/w 0 base address enable. gpio control registers if users want to access gpio configuration register, the inde x 07h of lpc global control registers must be write data 01h. when the base address enable register was write data 01h, the entry key will be unnecessary and users can get gpio port status or let gpio port output data immediately.
dec,2011 v0.13p - 18 - f75113 ?-? reserved or tri-state gpio device configuration registers (ldn 01h) register 0x[hex] register name default value msb lsb 00 reserved - - - - - - - - 01 chip control register 0 0 0 0 0 0 1 0 02 gpio0x mode control register 0 0 0 0 0 0 0 0 03 gpio0x mode control register 0 0 0 0 0 0 0 0 04 gpio1x mode control register 0 0 0 0 0 0 0 0 05 gpio1x mode control register 0 0 0 0 0 0 0 0 06 gpio2x mode control register 0 0 0 0 0 0 0 0 08 wdt1 control register - - - - - 0 - 0 09 wdt1 count register 0 0 0 0 0 0 0 0 0a wdt2 control register - - 0 0 0 0 0 0 0b wdt2 count register 0 0 0 0 0 0 0 0 0c pd count register 0 1 1 0 0 0 1 1 0e reserved - - - - - - - - 0f reserved - - - - - - - - 10 chip control register 0 0 0 0 0 0 0 0 11 gpio0x output control register 0 0 0 0 0 0 0 0 12 gpio0x pin status register - - - - - - - - 13 gpio0x level / pulse control register 0 0 0 0 0 0 0 0 14 gpio0x pulse width control register - - - - - - 0 0 15 gpio0x internal pull-high enable register 0 0 0 0 0 0 0 0 16 gpio0x debounce enable register 0 0 0 0 0 0 0 0 17 gpio0x pin inverse enable register 0 0 0 0 0 0 0 0 18 gpio0x edge detect enable register 0 0 0 0 0 0 0 0 19 gpio0x edge detect status register 0 0 0 0 0 0 0 0 1a smi event of gpio0x port enable register 0 0 0 0 0 0 0 0 1b gpio0x output buffer enable register 0 0 0 0 0 0 0 0 1c gpio0x debounce timing select register 0 0 0 0 0 0 0 0 1d led0x frequency select register 0 0 0 0 0 0 0 0 1e led0x frequency select register 0 0 0 0 0 0 0 0 20 gpio1x output control register 0 0 0 0 0 0 0 0 21 gpio1x output control register 0 0 0 0 0 0 0 0 22 gpio1x pin status register - - - - - - - -
dec,2011 v0.13p - 19 - f75113 23 gpio1x level / pulse control register 0 0 0 0 0 0 0 0 24 gpio1x pulse width control register - - - - - - 0 0 25 gpio1x internal pull-high enable register 0 0 0 0 0 0 0 0 26 gpio1x debounce enable register 0 0 0 0 0 0 0 0 27 gpio1x pin inverse enable register 0 0 0 0 0 0 0 0 28 gpio1x edge detect enable register 0 0 0 0 0 0 0 0 29 gpio1x edge detect status register 0 0 0 0 0 0 0 0 2a smi event of gpio1x port enable register 0 0 0 0 0 0 0 0 2b gpio1x output buffer enable register 0 0 0 0 0 0 0 0 2c gpio1x debounce timing select register 0 0 0 0 0 0 0 0 2d led1x frequency select register 0 0 0 0 0 0 0 0 2e led1x frequency select register 0 0 0 0 0 0 0 0 30 gpio2x output control register 0 0 0 0 0 0 0 0 31 gpio2x output control register 0 0 0 0 0 0 0 0 32 gpio2x pin status register - - - - - - - - 33 gpio2x level / pulse control register 0 0 0 0 0 0 0 0 34 gpio2x pulse width control register - - - - - - 0 0 35 gpio2x internal pull-high enable register 0 0 0 0 0 0 0 0 36 gpio2x debounce enable register 0 0 0 0 0 0 0 0 37 gpio2x pint inverse enable register 0 0 0 0 0 0 0 0 38 gpio2x edge detect enable register 0 0 0 0 0 0 0 0 39 gpio2x edge detect status register 0 0 0 0 0 0 0 0 3a smi event of gpio2x port enable register 0 0 0 0 0 0 0 0 3b gpio2x output buffer enable register 0 0 0 0 0 0 0 0 3c gpio2x debounce timing select register 0 0 0 0 0 0 0 0 3d led2x frequency select register 0 0 0 0 0 0 0 0 3e led2x frequency select register 0 0 0 0 0 0 0 0 3f gpio2x low level input enable register 0 0 0 0 0 0 0 0 40 gpio3x output control register 0 0 0 0 0 0 0 0 41 gpio3x output control register 0 0 0 0 0 0 0 0 42 gpio3x pin status register - - - - - - - - 43 gpio3x level / pulse control register 0 0 0 0 0 0 0 0 44 gpio3x pulse width control register - - - - - - 0 0 45 gpio3x internal pull-high enable register 0 0 0 0 0 0 0 0 46 gpio3x debounce enable register 0 0 0 0 0 0 0 0 47 gpio3x pin inverse enable register 0 0 0 0 0 0 0 0
dec,2011 v0.13p - 20 - f75113 48 gpio3x edge detect enable register 0 0 0 0 0 0 0 0 49 gpio3x edge detect status register 0 0 0 0 0 0 0 0 4a smi event of gpio3x port enable register 0 0 0 0 0 0 0 0 4b gpio3x output buffer enable register 0 0 0 0 0 0 0 0 4c gpio3x debounce timing select register 0 0 0 0 0 0 0 0 50 gpio port edge status register - - - 0 0 0 0 0 51 sirq enable register - - - 0 0 0 0 0 52 sirq channel select0 register 0 0 0 0 0 0 0 0 53 sirq channel select1 register 0 0 0 0 0 0 0 0 54 sirq channel select2 register 0 - - - 0 0 0 0 56 access function internal pull-up enable register 0 0 0 0 0 0 0 0 57 wdt1 reset gpio function enable register 0 0 0 0 0 0 0 0 58 wdt2 reset gpio function enable register 0 0 0 0 0 0 0 0 59 lreset reset gpio function e nable register 0 0 0 0 0 0 0 0 5a chip id1 0 0 0 1 0 0 0 0 5b chip id2 0 0 0 1 0 0 0 1 5d vender id1 0 0 0 1 1 0 0 1 5e vender id2 0 0 1 1 0 1 0 0 60 base address high-byte register 0 0 0 0 0 0 0 0 61 base address low-byte register 0 0 0 0 0 0 0 0 70 gpio4x output control register 0 0 0 0 0 0 0 0 71 gpio4x output control register 0 0 0 0 0 0 0 0 72 gpio4x pin status register - - - - - - - - 73 gpio4x level / pulse control register 0 0 0 0 0 0 0 0 74 gpio4x pulse width control register - - - - - - 0 0 75 gpio4x internal pull-high enable register 0 0 0 0 0 0 0 0 76 gpio4x debounce enable register 0 0 0 0 0 0 0 0 77 gpio4x pin inverse enable register 0 0 0 0 0 0 0 0 78 gpio4x edge detect enable register 0 0 0 0 0 0 0 0 79 gpio4x edge detect status register 0 0 0 0 0 0 0 0 7a smi event of gpio4x port enable register 0 0 0 0 0 0 0 0 7b gpio4x output buffer enable register 0 0 0 0 0 0 0 0 7c gpio4x debounce timing select register 0 0 0 0 0 0 0 0 80-8e reserved - - - - - - - -
dec,2011 v0.13p - 21 - f75113 8.2.1 chip control register ? index 01h bit name r/w default description 7 pd_stus r 0 power down status 6 wdt2out_en r/w 0 if the bit is set to 1, wdt2 resetout signal will output from gpio04~gpio07 pin. 5 wdt1out_en r/w 0 if the bit is set to 1, wdt1 resetout signal will output from gpio00~gpio03 pin. 4 smiout_en r/w 0 if the bit is set to 1, smi signal will output from gpio0x port. 3 sel_smi_width r/w 0 0: smi pulse width is 200usec. 1: smi pulse width is 150msec. 2 smi_md r/w 0 smi output mode is level or pulse mode. 0: level mode 1: pulse mode 1 smart_pd_md r/w 1 set this bit to 1 will enable auto power down mode, when all function are idle then 10ms, the chip will auto power down. it will wakeup when gpio state change or read write register 0 manual_pd r/w 0 set this bit to 1 will power down all of the analog block and stop internal clock, write 0 to clear this bit or when gpio state change will auto clear this bit to 0. 8.2.2 gpio0x mode control register ? index 02h bit name r/w default description 7-6 gpio07_md r/w 0 00b: gpio07 pin is gpio function. 01b: gpio07 pin is led function. 10b: gpio07 pin is smi function. 11b: gpio07 pin is rstout2. 5-4 gpio06_md r/w 0 00b: gpio06 pin is gpio function. 01b: gpio06 pin is led function. 10b: gpio06 pin is smi function. 11b: gpio06 pin is rstout2.
dec,2011 v0.13p - 22 - f75113 3-2 gpio05_md r/w 0 00b: gpio05 pin is gpio function. 01b: gpio05 pin is led function. 10b: gpio05 pin is smi function. 11b: gpio05 pin is rstout2. 1-0 gpio04_md r/w 0 00b: gpio04 pin is gpio function. 01b: gpio04 pin is led function. 10b: gpio04 pin is smi function. 11b: gpio04 pin is rstout2. 8.2.3 gpio1x mode control register ? index 03h bit name r/w default description 7-6 gpio03_md r/w 0 00b: gpio03 pin is gpio function. 01b: gpio03 pin is led function. 10b: gpio03 pin is smi function. 11b: gpio03 pin is rstout1. 5-4 gpio02_md r/w 0 00b: gpio02 pin is gpio function. 01b: gpio02 pin is led function. 10b: gpio02 pin is smi function. 11b: gpio02 pin is rstout1. 3-2 gpio01_md r/w 0 00b: gpio01 pin is gpio function. 01b: gpio01 pin is led function. 10b: gpio01 pin is smi function. 11b: gpio01 pin is rstout1. 1-0 gpio00_md r/w 0 00b: gpio00 pin is gpio function. 01b: gpio00 pin is led function. 10b: gpio00 pin is smi function. 11b: gpio00 pin is rstout1.
dec,2011 v0.13p - 23 - f75113 8.2.4 gpio1x mode control register ? index 04h bit name r/w default description 7-6 gpio17_md r/w 0 00b: gpio17 pin is gpio function. 01b: gpio17 pin is led function. 10b: reserved 11b: reserved 5-4 gpio16_md r/w 0 00b: gpio16 pin is gpio function. 01b: gpio16 pin is led function. 10b: reserved 11b: reserved 3-2 gpio15_md r/w 0 00b: gpio15 pin is gpio function. 01b: gpio15 pin is led function. 10b: reserved 11b: reserved 1-0 gpio14_md r/w 0 00b: gpio14 pin is gpio function. 01b: gpio14 pin is led function. 10b: reserved 11b: reserved 8.2.5 gpio1x mode control register ? index 05h bit name r/w default description 7-6 gpio13_md r/w 0 00b: gpio13 pin is gpio function. 01b: gpio13 pin is led function. 10b: reserved 11b: reserved 5-4 gpio12_md r/w 0 00b: gpio12 pin is gpio function. 01b: gpio12 pin is led function. 10b: reserved 11b: reserved
dec,2011 v0.13p - 24 - f75113 3-2 gpio11_md r/w 0 00b: gpio11 pin is gpio function. 01b: gpio11 pin is led function. 10b: reserved 11b: reserved 1-0 gpio10_md r/w 0 00b: gpio10 pin is gpio function. 01b: gpio10 pin is led function. 10b: reserved 11b: reserved 8.2.6 gpio2x mode control register ? index 06h bit name r/w default description 7 gpio27_md r/w 0 0b: gpio27 pin is gpio function. 1b: gpio27 pin is led function. 6 gpio26_md r/w 0 0b: gpio26 pin is gpio function. 1b: gpio26 pin is led function. 5 gpio25_md r/w 0 0b: gpio25 pin is gpio function. 1b: gpio25 pin is led function. 4 gpio24_md r/w 0 0b: gpio24 pin is gpio function. 1b: gpio24 pin is led function. 3 gpio23_md r/w 0 0b: gpio23 pin is gpio function. 1b: gpio23 pin is led function. 2 gpio22_md r/w 0 0b: gpio22 pin is gpio function. 1b: gpio22 pin is led function. 1 gpio21_md r/w 0 0b: gpio21 pin is gpio function. 1b: gpio21 pin is led function. 0 gpio20_md r/w 0 0b: gpio20 pin is gpio function. 1b: gpio20 pin is led function.
dec,2011 v0.13p - 25 - f75113 8.2.7 wdt1 control register ? index 08h bit name r/w default description 7-3 reserved - - reserved 2 sel_rstout_pw r/w 0 0b: rstout pulse width for wdt1 is 500usec 1b: rstout pulse width for wdt1 is 100msec 1 reserved - - reserved 0 wdt1_rst_st r 0 wdt1 rstout status. write 1 to clear the bit. 8.2.8 wdt1 count register ? index 09h bit name r/w default description 7 wdt1_en r/w 0 0b: disable wdt1 count. 1b: enable wdt1 count. 6-0 wdt1_time r /w 0 watchdog1 timing range from 0 ~ 127sec. 0000000b: 0sec 0000001b: 1sec ? 1111111b: 127sec 8.2.9 wdt2 control register ? index 0ah bit name r/w default description 7-6 reserved - - reserved 5 wdt2_rst_st r 0 wdt2 rstout status. write 1 to clear the bit. 4 wdt2_en r/w 0 0b: disable wdt2 count. 1b: enable wdt2 count. 3 wdt2_ps_en r/w 0 0b: level mode 1b: wdt2 pulse mode output enable. 2 wdt2_unit r/w 0 wdt2 unit select. default 0 is select second. write 1 to select minute.
dec,2011 v0.13p - 26 - f75113 1-0 wdt2_pw r/w 0 active width of pulse mode. 00b: pulse width is 1msec. 01b: pulse width is 20msec. 10b: pulse width is 100msec 11b: pulse width is 5sec. 8.2.10 wdt2 count register ? index 0bh bit name r/w default description 7-0 wdt2_timie r/w 00h wdt1 timing range from 0 ~ 255. 00000000b: 0 (second/minute) 00000001b: 1 (second/minute) ? 11111111b: 255(second/minute) the unit is either second or minute programmed by the watchdog timer control register bit2 in index 0ah. 8.2.11 power down count register ? index 0ch bit name r/w default description 7-0 pd_time r/w 63h power down timing range from 0 ~ 25.6msec. ex: 01100011b: 10msec(default) 11000111b: 20msec 11111111b: 25.6msec 8.2.12 gpio0x output control register ? index 10h bit name r/w default description 7 gp07_octrl r/w 0 gpio07 output control. 1 : output. 0 : input (default).
dec,2011 v0.13p - 27 - f75113 6 gp06_octrl r/w 0 gpio06 output control. 1 : output. 0 : input (default). 5 gp05_octrl r/w 0 gpio05 output control. 1 : output. 0 : input (default). 4 gp04_octrl r/w 0 gpio04 output control. 1 : output. 0 : input (default). 3 gp03_octrl r/w 0 gpio03 output control. 1 : output. 0 : input (default). 2 gp02_octrl r/w 0 gpio02 output control. 1 : output. 0 : input (default). 1 gp01_octrl r/w 0 gpio01 output control. 1 : output. 0 : input (default). 0 gp00_octrl r/w 0 gpio00 output control. 1 : output. 0 : input (default). 8.2.13 gpio0x output data register ? index 11h bit name r/w default description 7 gp07_ odata r/w 0 gpio07 output data. 6 gp06_ odata r/w 0 gpio06 output data. 5 gp05_ odata r/w 0 gpio05 output data. 4 gp04_ odata r/w 0 gpio04 output data. 3 gp03_ odata r/w 0 gpio03 output data. 2 gp02_ odata r/w 0 gpio02 output data. 1 gp01_ odata r/w 0 gpio01 output data. 0 gp00_ odata r/w 0 gpio00 output data.
dec,2011 v0.13p - 28 - f75113 8.2.14 gpio0x input status register ? index 12h bit name r/w default description 7 gp07_ psts r - read the gpio07 data on the pin. 6 gp06_ psts r - read the gpio06 data on the pin. 5 gp05_ psts r - read the gpio05 data on the pin. 4 gp04_ psts r - read the gpio04 data on the pin. 3 gp03_ psts r - read the gpio03 data on the pin. 2 gp02_ psts r - read the gpio02 data on the pin. 1 gp01_ psts r - read the gpio01 data on the pin. 0 gp00_psts r - read the gpio00 data on the pin. 8.2.15 gpio0x level/pulse control register ? index 13h bit name r/w default description 7 gp07_ omode r/w 0 gpio07 output mode. 0 ? level, 1 ? pulse. 6 gp06_ omode r/w 0 gpio06 output mode. 0 ? level, 1 ? pulse. 5 gp05_ omode r/w 0 gpio05 output mode. 0 ? level, 1 ? pulse. 4 gp04_ omode r/w 0 gpio04 output mode. 0 ? level, 1 ? pulse. 3 gp03_ omode r/w 0 gpio03 output mode. 0 ? level, 1 ? pulse. 2 gp02_ omode r/w 0 gpio02 output mode. 0 ? level, 1 ? pulse. 1 gp01_ omode r/w 0 gpio01 output mode. 0 ? level, 1 ? pulse. 0 gp00_ omode r/w 0 gpio00 output mode. 0 ? level, 1 ? pulse. 8.2.16 gpio0x pulse width control register ? index 14h bit name r/w default description 7-2 reserved - - reserved 1-0 gp0_plswd r/w 0 gpio0x pulse width. if set the gpio0x to pulse mode, the pulse width can be defined as follows. 00b ? 500us (default) 01b ? 1ms 10b ? 20ms 11b ? 100ms
dec,2011 v0.13p - 29 - f75113 8.2.17 gpio0x pull-up resistor control register ? index 15h bit name r/w default description 7 gp07_ reson r/w 0 turn on the gpio07 pin internal pull-up resistor with 10k ? . 6 gp06_ reson r/w 0 turn on the gpio06 pin internal pull-up resistor with 10k ? . 5 gp05_ reson r/w 0 turn on the gpio05 pin internal pull-up resistor with 10k ? . 4 gp04_ reson r/w 0 turn on the gpio04 pin internal pull-up resistor with 10k ? . 3 gp03_ reson r/w 0 turn on the gpio03 pin internal pull-up resistor with 10k ? . 2 gp02_ reson r/w 0 turn on the gpio02 pin internal pull-up resistor with 10k ? . 1 gp01_ reson r/w 0 turn on the gpio01 pin internal pull-up resistor with 10k ? . 0 gp00_ reson r/w 0 turn on the gpio00 pin internal pull-up resistor with 10k ? . 8.2.18 gpio0x input de-bounce register ? index 16h bit name r/w default description 7 gp07_ endb r/w 0 enable gpio07 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit7 . 6 gp06_ endb r/w 0 enable gpio06 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit6 . 5 gp05_ endb r/w 0 enable gpio05 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit5. 4 gp04_ endb r/w 0 enable gpio04 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit4. 3 gp03_ endb r/w 0 enable gpio03 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit3 .
dec,2011 v0.13p - 30 - f75113 2 gp02_ endb r/w 0 enable gpio02 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit2 . 1 gp01_ endb r/w 0 enable gpio01 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit1 . 0 gp00_ endb r/w 0 enable gpio00 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 1ch bit0. 8.2.19 gpio0x pin inverse enable register ? index 17h bit name r/w default description 7 gp07_ pinv r/w 0 if the gpio07 pin inverse was sele cted, the output signal would be inversed. 6 gp06_ pinv r/w 0 if the gpio06 pin inverse was sele cted, the output signal would be inversed. 5 gp05_ pinv r/w 0 if the gpio05 pin inverse was sele cted, the output signal would be inversed. 4 gp04_ pinv r/w 0 if the gpio04 pin inverse was sele cted, the output signal would be inversed. 3 gp03_ pinv r/w 0 if the gpio03 pin inverse was sele cted, the output signal would be inversed. 2 gp02_ pinv r/w 0 if the gpio02 pin inverse was sele cted, the output signal would be inversed. 1 gp01_ pinv r/w 0 if the gpio01 pin inverse was sele cted, the output signal would be inversed. 0 gp00_ pinv r/w 0 if the gpio00 pin inverse was sele cted, the output signal would be inversed.
dec,2011 v0.13p - 31 - f75113 8.2.20 gpio0x edge detector enable register ? index 18h bit name r/w default description 7 en_gp07edge r/w 0 enable gpio07 edge detector. if this bit set to 1 and gpio07 set to input mode (10h) will enable gpio07 edge detection. default is disabled. 6 en_gp06edge r/w 0 enable gpio06 edge detector. if this bit set to 1 and gpio06 set to input mode (10h) will enable gpio06 edge detection. default is disabled. 5 en_gp05edge r/w 0 enable gpio05 edge detector. if this bit set to 1 and gpio05 set to input mode (10h) will enable gpio05 edge detection. default is disabled. 4 en_gp04edge r/w 0 enable gpio04 edge detector. if this bit set to 1 and gpio04 set to input mode (10h) will enable gpio04 edge detection. default is disabled. 3 en_gp03edge r/w 0 enable gpio03 edge detector. if this bit set to 1 and gpio03 set to input mode (10h) will enable gpio03 edge detection. default is disabled. 2 en_gp02edge r/w 0 enable gpio02 edge detector. if this bit set to 1 and gpio02 set to input mode (10h) will enable gpio02 edge detection. default is disabled. 1 en_gp01edge r/w 0 enable gpio01 edge detector. if this bit set to 1 and gpio01 set to input mode (10h) will enable gpio01 edge detection. default is disabled. 0 en_gp00edge r/w 0 enable gpio00 edge detector. if this bit set to 1 and gpio00 set to input mode (10h) will enable gpio00 edge detection. default is disabled. 8.2.21 gpio0x edge detector status register ? index 19h bit name r/w default description 7 sts_gp07edge r - indicate gpio07 edge status. if set to 1, the edge of gpio07 has occurred. write 1 to clear this bit. writing 0 is invalid. 6 sts_gp06edge r - indicate gpio06 edge status. if set to 1, the edge of gpio06 has occurred. write 1 to clear this bit. writing 0 is invalid.
dec,2011 v0.13p - 32 - f75113 5 sts_gp05edge r - indicate gpio05 edge status. if set to 1, the edge of gpio05 has occurred. write 1 to clear this bit. writing 0 is invalid. 4 sts_gp04edge r - indicate gpio04 edge status. if set to 1, the edge of gpio04 has occurred. write 1 to clear this bit. writing 0 is invalid. 3 sts_gp03edge r - indicate gpio03 edge status. if set to 1, the edge of gpio03 has occurred. write 1 to clear this bit. writing 0 is invalid. 2 sts_gp02edge r - indicate gpio02 edge status. if set to 1, the edge of gpio02 has occurred. write 1 to clear this bit. writing 0 is invalid. 1 sts_gp01edge r - indicate gpio01 edge status. if set to 1, the edge of gpio01 has occurred. write 1 to clear this bit. writing 0 is invalid. 0 sts_gp00edge r - indicate gpio00 edge status. if set to 1, the edge of gpio00 has occurred. write 1 to clear this bit. writing 0 is invalid. 8.2.22 gpio0x smi enable register ? index 1ah bit name r/w default description 7 en_gp07smi r/w 0 enable gpio07 smi generation. if this bit set to 1, enable gpio07 to generate smi. 6 en_gp06smi r/w 0 enable gpio06 smi generation. if this bit set to 1, enable gpio06 to generate smi. 5 en_gp05smi r/w 0 enable gpio05 smi generation. if this bit set to 1, enable gpio05 to generate smi. 4 en_gp04smi r/w 0 enable gpio04 smi generation. if this bit set to 1, enable gpio04 to generate smi. 3 en_gp03smi r/w 0 enable gpio03 smi generation. if this bit set to 1, enable gpio03 to generate smi. 2 en_gp02smi r/w 0 enable gpio02 smi generation. if this bit set to 1, enable gpio02 to generate smi. 1 en_gp01smi r/w 0 enable gpio01 smi generation. if this bit set to 1, enable gpio01 to generate smi. 0 en_gp00smi r/w 0 enable gpio00 smi generation. if this bit set to 1, enable gpio00 to generate smi.
dec,2011 v0.13p - 33 - f75113 8.2.23 gpio0x output driving enable register ? index 1bh bit name r/w default description 7 en_gp07_obuf r/w 0 enable gpio07 drive high buffer. if this bit is set to 0, the pin gpio07 will be i/od pin, if set to 1 the pin gpio07 is i/o pin. 6 en_gp06_obuf r/w 0 enable gpio06 drive high buffer. if this bit is set to 0, the pin gpio06 will be i/od pin, if set to 1 the pin gpio06 is i/o pin. 5 en_gp05_obuf r/w 0 enable gpio05 drive high buffer. if this bit is set to 0, the pin gpio05 will be i/od pin, if set to 1 the pin gpio05 is i/o pin. 4 en_gp04_obuf r/w 0 enable gpio04 drive high buffer. if this bit is set to 0, the pin gpio04 will be i/od pin, if set to 1 the pin gpio04 is i/o pin. 3 en_gp03_obuf r/w 0 enable gpio03 drive high buffer. if this bit is set to 0, the pin gpio03 will be i/od pin, if set to 1 the pin gpio03 is i/o pin. 2 en_gp02_obuf r/w 0 enable gpio02 drive high buffer. if this bit is set to 0, the pin gpio02 will be i/od pin, if set to 1 the pin gpio02 is i/o pin. 1 en_gp01_obuf r/w 0 enable gpio01 drive high buffer. if this bit is set to 0, the pin gpio01 will be i/od pin, if set to 1 the pin gpio01 is i/o pin. 0 en_gp00_obuf r/w 0 enable gpio00 drive high buffer. if this bit is set to 0, the pin gpio00 will be i/od pin, if set to 1 the pin gpio00 is i/o pin. 8.2.24 gpio0x de-bounce time select register ? index 1ch bit name r/w default description 7 db_time07_sel r/w 0 select gpio07 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 6 db_time06_sel r/w 0 select gpio06 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 5 db_time05_sel r/w 0 select gpio05 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 4 db_time04_sel r/w 0 select gpio04 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 3 db_time03_sel r/w 0 select gpio03 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 34 - f75113 2 db_time02_sel r/w 0 select gpio02 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 1 db_time01_sel r/w 0 select gpio01 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 0 db_time00_sel r/w 0 select gpio00 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 8.2.25 led0x frequency select register ? index 1dh bit name r/w default description 7-6 led07_freq r/w 0 led07 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led06_freq r/w 0 led06 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led05_freq r/w 0 led05 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led04_freq r/w 0 led04 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%)
dec,2011 v0.13p - 35 - f75113 8.2.26 led0x frequency select register ? index 1eh bit name r/w default description 7-6 led03_freq r/w 0 led03 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led02_freq r/w 0 led02 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led01_freq r/w 0 led01 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led00_freq r/w 0 led00 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 8.2.27 gpio1x output control register ? index 20h bit name r/w default description 7 gp17_octrl r/w 0 gpio17 output control. set to 1 for output function. set to 0 for input function (default). 6 gp16_octrl r/w 0 gpio16 output control. set to 1 for output function. set to 0 for input function (default).
dec,2011 v0.13p - 36 - f75113 5 gp15_octrl r/w 0 gpio15 output control. set to 1 for output function. set to 0 for input function (default). 4 gp14_octrl r/w 0 gpio14 output control. set to 1 for output function. set to 0 for input function (default). 3 gp13_octrl r/w 0 gpio13 output control. set to 1 for output function. set to 0 for input function (default). 2 gp12_octrl r/w 0 gpio12 output control. set to 1 for output function. set to 0 for input function (default). 1 gp11_octrl r/w 0 gpio11 output control. set to 1 for output function. set to 0 for input function (default). 0 gp10_octrl r/w 0 gpio10 output control. set to 1 for output function. set to 0 for input function (default). 8.2.28 gpio1x output data register ? index 21h bit name r/w default description 7 gp17_ odata r/w 0 gpio17 output data. 6 gp16_ odata r/w 0 gpio16 output data. 5 gp15_ odata r/w 0 gpio15 output data. 4 gp14_ odata r/w 0 gpio14 output data. 3 gp13_ odata r/w 0 gpio13 output data. 2 gp12_ odata r/w 0 gpio12 output data. 1 gp11_ odata r/w 0 gpio11 output data. 0 gp10_ odata r/w 0 gpio10 output data. 8.2.29 gpio1x input status register ? index 22h bit name r/w default description 7 gp17_ psts r - read the gpio17 data on the pin. 6 gp16_ psts r - read the gpio16 data on the pin. 5 gp15_ psts r - read the gpio15 data on the pin. 4 gp14_ psts r - read the gpio14 data on the pin. 3 gp13_ psts r - read the gpio13 data on the pin.
dec,2011 v0.13p - 37 - f75113 2 gp12_ psts r - read the gpio12 data on the pin. 1 gp11_ psts r - read the gpio11 data on the pin. 0 gp10_psts r - read the gpio10 data on the pin. 8.2.30 gpio1x level/pulse control register ? index 23h bit name r/w default description 7 gp17_ omode r/w 0 gpio17 output mode. 0 ? level, 1 ? pulse. 6 gp16_ omode r/w 0 gpio16 output mode. 0 ? level, 1 ? pulse. 5 gp15_ omode r/w 0 gpio15 output mode. 0 ? level, 1 ? pulse. 4 gp14_ omode r/w 0 gpio14 output mode. 0 ? level, 1 ? pulse. 3 gp13_ omode r/w 0 gpio13 output mode. 0 ? level, 1 ? pulse. 2 gp12_ omode r/w 0 gpio12 output mode. 0 ? level, 1 ? pulse. 1 gp11_ omode r/w 0 gpio11 output mode. 0 ? level, 1 ? pulse. 0 gp10_ omode r/w 0 gpio10 output mode. 0 ? level, 1 ? pulse. 8.2.31 gpio1x pulse width control register ? index 24h bit name r/w default description 7-2 reserved - - reserved 1-0 gp1_plswd r/w 00b gpio1x pulse width. if set the gpio1x to pulse mode, the pulse width can be defined as follows. 00b ? 500us (default) 01b ? 1ms 10b ? 20ms 11b ? 100ms 8.2.32 gpio1x pull-up resistor control register ? index 25h bit name r/w default description 7 gp17_ reson r/w 0 turn on the gpio17 pin internal pull-up resistor with 10k ? . 6 gp16_ reson r/w 0 turn on the gpio16 pin internal pull-up resistor with 10k ? . 5 gp15_ reson r/w 0 turn on the gpio15 pin internal pull-up resistor with 10k ? . 4 gp14_ reson r/w 0 turn on the gpio14 pin internal pull-up resistor with 10k ? . 3 gp13_ reson r/w 0 turn on the gpio13 pin internal pull-up resistor with 10k ? .
dec,2011 v0.13p - 38 - f75113 2 gp12_ reson r/w 0 turn on the gpio12 pin internal pull-up resistor with 10k ? . 1 gp11_ reson r/w 0 turn on the gpio11 pin internal pull-up resistor with 10k ? . 0 gp10_ reson r/w 0 turn on the gpio10 pin internal pull-up resistor with 10k ? . 8.2.33 gpio1x input de-bounce register ? index 26h bit name r/w default description 7 gp17_ endb r/w 0 enable gpio17 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit7 . 6 gp16_ endb r/w 0 enable gpio16 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit6 . 5 gp15_ endb r/w 0 enable gpio15 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit5. 4 gp14_ endb r/w 0 enable gpio14 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit4 . 3 gp13_ endb r/w 0 enable gpio13 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit3 . 2 gp12_ endb r/w 0 enable gpio12 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit2. 1 gp11_ endb r/w 0 enable gpio11 input de-bounce with 10u (maximum, when input signal and detected clock is sy nchronicity) or 25ms (maximum, when input signal and detected cl ock is synchronicity) second that selected by 2ch bit1 .
dec,2011 v0.13p - 39 - f75113 0 gp10_ endb r/w 0 enable gpio10 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 2ch bit0. 8.2.34 gpio1x pin inverse enable register ? index 27h bit name r/w default description 7 gp17_ pinv r/w 0 if the gpio17 pin inverse was sele cted, the output signal would be inversed. 6 gp16_ pinv r/w 0 if the gpio16 pin inverse was sele cted, the output signal would be inversed. 5 gp15_ pinv r/w 0 if the gpio15 pin inverse was sele cted, the output signal would be inversed. 4 gp14_ pinv r/w 0 if the gpio14 pin inverse was sele cted, the output signal would be inversed. 3 gp13_ pinv r/w 0 if the gpio13 pin inverse was sele cted, the output signal would be inversed. 2 gp12_ pinv r/w 0 if the gpio12 pin inverse was sele cted, the output signal would be inversed. 1 gp11_ pinv r/w 0 if the gpio11 pin inverse was selected, the output signal would be inversed. 0 gp10_ pinv r/w 0 if the gpio10 pin inverse was sele cted, the output signal would be inversed. 8.2.35 gpio1x edge detector enable register ? index 28h bit name r/w default description 7 en_gp17edge r/w 0 enable gpio17 edge detector. if this bit set to 1 and gpio17 set to input mode (20h) will enable gpio17 edge detection. default is disabled. 6 en_gp16edge r/w 0 enable gpio16 edge detector. if this bit set to 1 and gpio16 set to input mode (20h) will enable gpio16 edge detection. default is disabled.
dec,2011 v0.13p - 40 - f75113 5 en_gp15edge r/w 0 enable gpio15 edge detector. if this bit set to 1 and gpio15 set to input mode (20h) will enable gpio15 edge detection. default is disabled. 4 en_gp14edge r/w 0 enable gpio14 edge detector. if this bit set to 1 and gpio14 set to input mode (20h) will enable gpio14 edge detection. default is disabled. 3 en_gp13edge r/w 0 enable gpio13 edge detector. if this bit set to 1 and gpio13 set to input mode (20h) will enable gpio13 edge detection. default is disabled. 2 en_gp12edge r/w 0 enable gpio12 edge detector. if this bit set to 1 and gpio12 set to input mode (20h) will enable gpio12 edge detection. default is disabled. 1 en_gp11edge r/w 0 enable gpio11 edge detector. if this bit set to 1 and gpio11 set to input mode (20h) will enable gpio11 edge detection. default is disabled. 0 en_gp10edge r/w 0 enable gpio10 edge detector. if this bit set to 1 and gpio10 set to input mode (20h) will enable gpio10 edge detection. default is disabled. 8.2.36 gpio1x edge detector status register ? index 29h bit name r/w default description 7 sts_gp17edge r - indicate gpio17 edge status. if set to 1, the edge of gpio17 has occurred. write 1 to clear this bit. writing 0 is invalid. 6 sts_gp16edge r - indicate gpio16 edge status. if set to 1, the edge of gpio16 has occurred. write 1 to clear this bit. writing 0 is invalid. 5 sts_gp15edge r - indicate gpio15 edge status. if set to 1, the edge of gpio15 has occurred. write 1 to clear this bit. writing 0 is invalid. 4 sts_gp14edge r - indicate gpio14 edge status. if set to 1, the edge of gpio14 has occurred. write 1 to clear this bit. writing 0 is invalid. 3 sts_gp13edge r - indicate gpio13 edge status. if set to 1, the edge of gpio13 has occurred. write 1 to clear this bit. writing 0 is invalid. 2 sts_gp12edge r - indicate gpio12 edge status. if set to 1, the edge of gpio12 has occurred. write 1 to clear this bit. writing 0 is invalid.
dec,2011 v0.13p - 41 - f75113 1 sts_gp11edge r - indicate gpio11 edge status. if set to 1, the edge of gpio11 has occurred. write 1 to clear this bit. writing 0 is invalid. 0 sts_gp10edge r - indicate gpio10 edge status. if set to 1, the edge of gpio10 has occurred. write 1 to clear this bit. writing 0 is invalid. 8.2.37 gpio1x smi enable register ? index 2ah bit name r/w default description 7 en_gp17smi r/w 0 enable gpio17 smi generation. if this bit set to 1, enable gpio17 to generate smi. 6 en_gp16smi r/w 0 enable gpio16 smi generation. if this bit set to 1, enable gpio16 to generate smi. 5 en_gp15smi r/w 0 enable gpio15 smi generation. if this bit set to 1, enable gpio15 to generate smi. 4 en_gp14smi r/w 0 enable gpio14 smi generation. if this bit set to 1, enable gpio14 to generate smi. 3 en_gp13smi r/w 0 enable gpio13 smi generation. if this bit set to 1, enable gpio13 to generate smi. 2 en_gp12smi r/w 0 enable gpio12 smi generation. if this bit set to 1, enable gpio12 to generate smi. 1 en_gp11smi r/w 0 enable gpio11 smi generation. if this bit set to 1, enable gpio11 to generate smi. 0 en_gp10smi r/w 0 enable gpio10 smi generation. if this bit set to 1, enable gpio10 to generate smi. 8.2.38 gpio1x output driving enable register ? index 2bh bit name r/w default description 7 en_gp17_obuf r/w 0 enable gpio17 drive high buffer. if this bit is set to 0, the pin gpio17 will be i/od pin, if set to 1 the pin gpio17 is i/o pin. 6 en_gp16_obuf r/w 0 enable gpio16 drive high buffer. if this bit is set to 0, the pin gpio16 will be i/od pin, if set to 1 the pin gpio16 is i/o pin. 5 en_gp15_obuf r/w 0 enable gpio15 drive high buffer. if this bit is set to 0, the pin gpio15 will be i/od pin, if set to 1 the pin gpio15 is i/o pin.
dec,2011 v0.13p - 42 - f75113 4 en_gp14_obuf r/w 0 enable gpio14 drive high buffer. if this bit is set to 0, the pin gpio14 will be i/od pin, if set to 1 the pin gpio14 is i/o pin. 3 en_gp13_obuf r/w 0 enable gpio13 drive high buffer. if this bit is set to 0, the pin gpio13 will be i/od pin, if set to 1 the pin gpio13 is i/o pin. 2 en_gp12_obuf r/w 0 enable gpio12 drive high buffer. if this bit is set to 0, the pin gpio12 will be i/od pin, if set to 1 the pin gpio12 is i/o pin. 1 en_gp11_obuf r/w 0 enable gpio11 drive high buffer. if this bit is set to 0, the pin gpio11 will be i/od pin, if set to 1 the pin gpio11 is i/o pin. 0 en_gp10_obuf r/w 0 enable gpio10 drive high buffer. if this bit is set to 0, the pin gpio10 will be i/od pin, if set to 1 the pin gpio10 is i/o pin. 8.2.39 gpio1x de-bounce time select register ? index 2ch bit name r/w default description 7 db_time17_sel r/w 0 select gpio17 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 6 db_time16_sel r/w 0 select gpio16 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 5 db_time15_sel r/w 0 select gpio15 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 4 db_time14_sel r/w 0 select gpio14 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 3 db_time13_sel r/w 0 select gpio13 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 2 db_time12_sel r/w 0 select gpio12 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 1 db_time11_sel r/w 0 select gpio11 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 0 db_time10_sel r/w 0 select gpio10 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 43 - f75113 8.2.40 led1x frequency select register ? index 2dh bit name r/w default description 7-6 led17_freq r/w 0 led17 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led16_freq r/w 0 led16 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led15_freq r/w 0 led15 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led14_freq r/w 0 led14 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%)
dec,2011 v0.13p - 44 - f75113 8.2.41 led1x frequency select register ? index 2eh bit name r/w default description 7-6 led13_freq r/w 0 led13 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led12_freq r/w 0 led12 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led11_freq r/w 0 led11 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led10_freq r/w 0 led10 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 8.2.42 gpio2x output control register ? index 30h bit name r/w default description 7 gp27_octrl r/w 0 gpio27 output control. set to 1 for output function. set to 0 for input function (default). 6 gp26_octrl r/w 0 gpio26 output control. set to 1 for output function. set to 0 for input function (default).
dec,2011 v0.13p - 45 - f75113 5 gp25_octrl r/w 0 gpio25 output control. set to 1 for output function. set to 0 for input function (default). 4 gp24_octrl r/w 0 gpio24 output control. set to 1 for output function. set to 0 for input function (default). 3 gp23_octrl r/w 0 gpio23 output control. set to 1 for output function. set to 0 for input function (default). 2 gp22_octrl r/w 0 gpio22 output control. set to 1 for output function. set to 0 for input function (default). 1 gp21_octrl r/w 0 gpio21 output control. set to 1 for output function. set to 0 for input function (default). 0 gp20_octrl r/w 0 gpio20 output control. set to 1 for output function. set to 0 for input function (default). 8.2.43 gpio2x output data register ? index 31h bit name r/w default description 7 gp27_ odata r/w 0 gpio27 output data. 6 gp26_ odata r/w 0 gpio26 output data. 5 gp25_ odata r/w 0 gpio25 output data. 4 gp24_ odata r/w 0 gpio24 output data. 3 gp23_ odata r/w 0 gpio23 output data. 2 gp22_ odata r/w 0 gpio22 output data. 1 gp21_ odata r/w 0 gpio21 output data. 0 gp20_ odata r/w 0 gpio20 output data. 8.2.44 gpio2x input status register ? index 32h bit name r/w default description 7 gp27_ psts r - read the gpio27 data on the pin. 6 gp26_ psts r - read the gpio26 data on the pin. 5 gp25_ psts r - read the gpio25 data on the pin. 4 gp24_ psts r - read the gpio24 data on the pin. 3 gp23_ psts r - read the gpio23 data on the pin.
dec,2011 v0.13p - 46 - f75113 2 gp22_ psts r - read the gpio22 data on the pin. 1 gp21_ psts r - read the gpio21 data on the pin. 0 gp20_psts r - read the gpio20 data on the pin. 8.2.45 gpio2x level/pulse control register ? index 33h bit name r/w default description 7 gp27_ omode r/w 0 gpio27 output mode. 0 ? level, 1 ? pulse. 6 gp26_ omode r/w 0 gpio26 output mode. 0 ? level, 1 ? pulse. 5 gp25_ omode r/w 0 gpio25 output mode. 0 ? level, 1 ? pulse. 4 gp24_ omode r/w 0 gpio24 output mode. 0 ? level, 1 ? pulse. 3 gp23_ omode r/w 0 gpio23 output mode. 0 ? level, 1 ? pulse. 2 gp22_ omode r/w 0 gpio22 output mode. 0 ? level, 1 ? pulse. 1 gp21_ omode r/w 0 gpio21 output mode. 0 ? level, 1 ? pulse. 0 gp20_ omode r/w 0 gpio20 output mode. 0 ? level, 1 ? pulse. 8.2.46 gpio2x pulse width control register ? index 34h bit name r/w default description 7-2 reserved - - reserved 1-0 gp2_plswd r/w 00b gpio2x pulse width. if set the gpio2x to pulse mode, the pulse width can be defined as follows. 00b ? 500us (default) 01b ? 1ms 10b ? 20ms 11b ? 100ms 8.2.47 gpio2x pull-up resistor control register ? index 35h bit name r/w default description 7 gp27_ reson r/w 0 turn on the gpio27 pin internal pull-up resistor with 10k ? . 6 gp26_ reson r/w 0 turn on the gpio26 pin internal pull-up resistor with 10k ? . 5 gp25_ reson r/w 0 turn on the gpio25 pin internal pull-up resistor with 10k ? . 4 gp24_ reson r/w 0 turn on the gpio24 pin internal pull-up resistor with 10k ? . 3 gp23_ reson r/w 0 turn on the gpio23 pin internal pull-up resistor with 10k ? .
dec,2011 v0.13p - 47 - f75113 2 gp22_ reson r/w 0 turn on the gpio22 pin internal pull-up resistor with 10k ? . 1 gp21_ reson r/w 0 turn on the gpio21 pin internal pull-up resistor with 10k ? . 0 gp20_ reson r/w 0 turn on the gpio20 pin internal pull-up resistor with 10k ? . 8.2.48 gpio2x input de-bounce register ? index 36h bit name r/w default description 7 gp27_ endb r/w 0 enable gpio27 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit7 . 6 gp26_ endb r/w 0 enable gpio26 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit6. 5 gp25_ endb r/w 0 enable gpio25 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit5 . 4 gp24_ endb r/w 0 enable gpio24 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit4. 3 gp23_ endb r/w 0 enable gpio23 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit3 . 2 gp22_ endb r/w 0 enable gpio22 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit2 . 1 gp21_ endb r/w 0 enable gpio21 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit1 .
dec,2011 v0.13p - 48 - f75113 0 gp20_ endb r/w 0 enable gpio20 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 3ch bit0. 8.2.49 gpio2x pin inverse enable register ? index37h bit name r/w default description 7 gp27_ pinv r/w 0 if the gpio27 pin inverse was sele cted, the output signal would be inversed. 6 gp26_ pinv r/w 0 if the gpio26 pin inverse was sele cted, the output signal would be inversed. 5 gp25_ pinv r/w 0 if the gpio25 pin inverse was sele cted, the output signal would be inversed. 4 gp24_ pinv r/w 0 if the gpio24 pin inverse was sele cted, the output signal would be inversed. 3 gp23_ pinv r/w 0 if the gpio23 pin inverse was sele cted, the output signal would be inversed. 2 gp22_ pinv r/w 0 if the gpio22 pin inverse was sele cted, the output signal would be inversed. 1 gp21_ pinv r/w 0 if the gpio21 pin inverse was sele cted, the output signal would be inversed. 0 gp20_ pinv r/w 0 if the gpio20 pin inverse was sele cted, the output signal would be inversed. 8.2.50 gpio2x edge detector enable register ? index 38h bit name r/w default description 7 en_gp27edge r/w 0 enable gpio27 edge detector. if this bit set to 1 and gpio27 set to input mode (30h) will enable gpio27 edge detection. default is disabled. 6 en_gp26edge r/w 0 enable gpio26 edge detector. if this bit set to 1 and gpio26 set to input mode (30h) will enable gpio26 edge detection. default is disabled.
dec,2011 v0.13p - 49 - f75113 5 en_gp25edge r/w 0 enable gpio25 edge detector. if this bit set to 1 and gpio25 set to input mode (30h) will enable gpio25 edge detection. default is disabled. 4 en_gp24edge r/w 0 enable gpio24 edge detector. if this bit set to 1 and gpio24 set to input mode (30h) will enable gpio24 edge detection. default is disabled. 3 en_gp23edge r/w 0 enable gpio23 edge detector. if this bit set to 1 and gpio23 set to input mode (30h) will enable gpio23 edge detection. default is disabled. 2 en_gp22edge r/w 0 enable gpio22 edge detector. if this bit set to 1 and gpio22 set to input mode (30h) will enable gpio22 edge detection. default is disabled. 1 en_gp21edge r/w 0 enable gpio21 edge detector. if this bit set to 1 and gpio21 set to input mode (30h) will enable gpio21 edge detection. default is disabled. 0 en_gp20edge r/w 0 enable gpio20 edge detector. if this bit set to 1 and gpio20 set to input mode (30h) will enable gpio20 edge detection. default is disabled. 8.2.51 gpio2x edge detector status register ? index 39h bit name r/w default description 7 sts_gp27edge r - indicate gpio27 edge status. if set to 1, the edge of gpio27 has occurred. write 1 to clear this bit. writing 0 is invalid. 6 sts_gp26edge r - indicate gpio26 edge status. if set to 1, the edge of gpio26 has occurred. write 1 to clear this bit. writing 0 is invalid. 5 sts_gp25edge r - indicate gpio25 edge status. if set to 1, the edge of gpio25 has occurred. write 1 to clear this bit. writing 0 is invalid. 4 sts_gp24edge r - indicate gpio24 edge status. if set to 1, the edge of gpio24 has occurred. write 1 to clear this bit. writing 0 is invalid. 3 sts_gp23edge r - indicate gpio23 edge status. if set to 1, the edge of gpio23 has occurred. write 1 to clear this bit. writing 0 is invalid. 2 sts_gp22edge r - indicate gpio22 edge status. if set to 1, the edge of gpio22 has occurred. write 1 to clear this bit. writing 0 is invalid.
dec,2011 v0.13p - 50 - f75113 1 sts_gp21edge r - indicate gpio21 edge status. if set to 1, the edge of gpio21 has occurred. write 1 to clear this bit. writing 0 is invalid. 0 sts_gp20edge r - indicate gpio20 edge status. if set to 1, the edge of gpio20 has occurred. write 1 to clear this bit. writing 0 is invalid. 8.2.52 gpio2x smi enable register ? index 3ah bit name r/w default description 7 en_gp27smi r/w 0 enable gpio27 smi generation. if this bit set to 1, enable gpio27 to generate smi. 6 en_gp26smi r/w 0 enable gpio26 smi generation. if this bit set to 1, enable gpio26 to generate smi. 5 en_gp25smi r/w 0 enable gpio25 smi generation. if this bit set to 1, enable gpio25 to generate smi. 4 en_gp24smi r/w 0 enable gpio24 smi generation. if this bit set to 1, enable gpio24 to generate smi. 3 en_gp23smi r/w 0 enable gpio23 smi generation. if this bit set to 1, enable gpio23 to generate smi. 2 en_gp22smi r/w 0 enable gpio22 smi generation. if this bit set to 1, enable gpio22 to generate smi. 1 en_gp21smi r/w 0 enable gpio21 smi generation. if this bit set to 1, enable gpio21 to generate smi. 0 en_gp20smi r/w 0 enable gpio20 smi generation. if this bit set to 1, enable gpio20 to generate smi. 8.2.53 gpio2x output driving enable register ? index 3bh bit name r/w default description 7 en_gp27_obuf r/w 0 enable gpio27 drive high buffer. if this bit is set to 0, the pin gpio27 will be i/od pin, if set to 1 the pin gpio27 is i/o pin. 6 en_gp26_obuf r/w 0 enable gpio26 drive high buffer. if this bit is set to 0, the pin gpio26 will be i/od pin, if set to 1 the pin gpio26 is i/o pin. 5 en_gp25_obuf r/w 0 enable gpio25 drive high buffer. if this bit is set to 0, the pin gpio25 will be i/od pin, if set to 1 the pin gpio25 is i/o pin.
dec,2011 v0.13p - 51 - f75113 4 en_gp24_obuf r/w 0 enable gpio24 drive high buffer. if this bit is set to 0, the pin gpio24 will be i/od pin, if set to 1 the pin gpio24 is i/o pin. 3 en_gp23_obuf r/w 0 enable gpio23 drive high buffer. if this bit is set to 0, the pin gpio23 will be i/od pin, if set to 1 the pin gpio23 is i/o pin. 2 en_gp22_obuf r/w 0 enable gpio22 drive high buffer. if this bit is set to 0, the pin gpio22 will be i/od pin, if set to 1 the pin gpio22 is i/o pin. 1 en_gp21_obuf r/w 0 enable gpio21 drive high buffer. if this bit is set to 0, the pin gpio21 will be i/od pin, if set to 1 the pin gpio21 is i/o pin. 0 en_gp20_obuf r/w 0 enable gpio20 drive high buffer. if this bit is set to 0, the pin gpio20 will be i/od pin, if set to 1 the pin gpio20 is i/o pin. 8.2.54 gpio2x de-bounce time select register ? index 3ch bit name r/w default description 7 db_time27_sel r/w 0 select gpio27 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 6 db_time26_sel r/w 0 select gpio26 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 5 db_time25_sel r/w 0 select gpio25 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 4 db_time24_sel r/w 0 select gpio24 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 3 db_time23_sel r/w 0 select gpio23 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 2 db_time22_sel r/w 0 select gpio22 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 1 db_time21_sel r/w 0 select gpio21 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 0 db_time20_sel r/w 0 select gpio20 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 52 - f75113 8.2.55 led2x frequency select register ? index 3dh bit name r/w default description 7-6 led27_freq r/w 0 led27 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led26_freq r/w 0 led26 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led25_freq r/w 0 led25 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led24_freq r/w 0 led24 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%)
dec,2011 v0.13p - 53 - f75113 8.2.56 led2x frequency select register ? index 3eh bit name r/w default description 7-6 led23_freq r/w 0 led23 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 5-4 led22_freq r/w 0 led22 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 3-2 led21_freq r/w 0 led21 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 1-0 led20_freq r/w 0 led20 output frequency. bit description 00b 0.25hz (default, duty cycle is 97.5%) 01b 0.5hz (duty cycle is 95%) 10b 1 hz (duty cycle is 90%) 11b 2hz (duty cycle is 80%) 8.2.2 gpio2x low level input enable register ? index 3fh bit name r/w default description 7 gp27_lvin_en r/w 0 enable gpio27 low level input detection. (v ih > 0.9v, v il <0.3v) 6 gp26_lvin_en r/w 0 enable gpio26 low level input detection. (v ih > 0.9v, v il <0.3v) 5 gp25_lvin_en r/w 0 enable gpio25 low level input detection. (v ih > 0.9v, v il <0.3v) 4 gp24_lvin_en r/w 0 enable gpio24 low level input detection. (v ih > 0.9v, v il <0.3v)
dec,2011 v0.13p - 54 - f75113 3 gp23_lvin_en r/w 0 enable gpio23 low level input detection. (v ih > 0.9v, v il <0.3v) 2 gp22_lvin_en r/w 0 enable gpio22 low level input detection. (v ih > 0.9v, v il <0.3v) 1 gp21_lvin_en r/w 0 enable gpio21 low level input detection. (v ih > 0.9v, v il <0.3v) 0 gp20_lvin_en r/w 0 enable gpio20 low level input detection. (v ih > 0.9v, v il <0.3v) 8.2.3 gpio3x output control register ? index 40h bit name r/w default description 7 gp37_octrl r/w 0 gpio37 output control. set to 1 for output function. set to 0 for input function (default). 6 gp36_octrl r/w 0 gpio36 output control. set to 1 for output function. set to 0 for input function (default). 5 gp35_octrl r/w 0 gpio35 output control. set to 1 for output function. set to 0 for input function (default). 4 gp34_octrl r/w 0 gpio34 output control. set to 1 for output function. set to 0 for input function (default). 3 gp33_octrl r/w 0 gpio33 output control. set to 1 for output function. set to 0 for input function (default). 2 gp32_octrl r/w 0 gpio32 output control. set to 1 for output function. set to 0 for input function (default). 1 gp31_octrl r/w 0 gpio31 output control. set to 1 for output function. set to 0 for input function (default). 0 gp30_octrl r/w 0 gpio30 output control. set to 1 for output function. set to 0 for input function (default). 8.2.4 gpio3x output data register ? index 41h bit name r/w default description 7 gp37_ odata r/w 0 gpio37 output data. 6 gp36_ odata r/w 0 gpio36 output data. 5 gp35_ odata r/w 0 gpio35 output data. 4 gp34_ odata r/w 0 gpio34 output data. 3 gp33_ odata r/w 0 gpio33 output data.
dec,2011 v0.13p - 55 - f75113 2 gp32_ odata r/w 0 gpio32 output data. 1 gp31_ odata r/w 0 gpio31 output data. 0 gp30_ odata r/w 0 gpio30 output data. 8.2.5 gpio3x input status register ? index 42h bit name r/w default description 7 gp37_ psts r - read the gpio37 data on the pin. 6 gp36_ psts r - read the gpio36 data on the pin. 5 gp35_ psts r - read the gpio35 data on the pin. 4 gp34_ psts r - read the gpio34 data on the pin. 3 gp33_ psts r - read the gpio33 data on the pin. 2 gp32_ psts r - read the gpio32 data on the pin. 1 gp31_ psts r - read the gpio31 data on the pin. 0 gp30_psts r - read the gpio30 data on the pin. 8.2.6 gpio3x level/pulse control register ? index 43h bit name r/w default description 7 gp37_ omode r/w 0 gpio37 output mode. 0 ? level, 1 ? pulse. 6 gp36_ omode r/w 0 gpio36 output mode. 0 ? level, 1 ? pulse. 5 gp35_ omode r/w 0 gpio35 output mode. 0 ? level, 1 ? pulse. 4 gp34_ omode r/w 0 gpio34 output mode. 0 ? level, 1 ? pulse. 3 gp33_ omode r/w 0 gpio33 output mode. 0 ? level, 1 ? pulse. 2 gp32_ omode r/w 0 gpio32 output mode. 0 ? level, 1 ? pulse. 1 gp31_ omode r/w 0 gpio31 output mode. 0 ? level, 1 ? pulse. 0 gp30_ omode r/w 0 gpio30 output mode. 0 ? level, 1 ? pulse. 8.2.7 gpio3x pulse width control register ? index 44h bit name r/w default description 7-2 reserved - - reserved
dec,2011 v0.13p - 56 - f75113 1-0 gp3_plswd r/w 00b gpio3x pulse width. if set the gpio3x to pulse mode, the pulse width can be defined as follows. 00b ? 500us (default) 01b ? 1ms 10b ? 20ms 11b ? 100ms 8.2.8 gpio3x pull-up resistor control register ? index 45h bit name r/w default description 7 gp37_ reson r/w 0 turn on the gpio37 pin internal pull-up resistor with 10k ? . 6 gp36_ reson r/w 0 turn on the gpio36 pin internal pull-up resistor with 10k ? . 5 gp35_ reson r/w 0 turn on the gpio35 pin internal pull-up resistor with 10k ? . 4 gp34_ reson r/w 0 turn on the gpio34 pin internal pull-up resistor with 10k ? . 3 gp33_ reson r/w 0 turn on the gpio33 pin internal pull-up resistor with 10k ? . 2 gp32_ reson r/w 0 turn on the gpio32 pin internal pull-up resistor with 10k ? . 1 gp31_ reson r/w 0 turn on the gpio31 pin internal pull-up resistor with 10k ? . 0 gp30_ reson r/w 0 turn on the gpio30 pin internal pull-up resistor with 10k ? . 8.2.9 gpio3x input de-bounce register ? index 46h bit name r/w default description 7 gp37_ endb r/w 0 enable gpio37 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit7 . 6 gp36_ endb r/w 0 enable gpio36 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit6 . 5 gp35_ endb r/w 0 enable gpio35 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit5.
dec,2011 v0.13p - 57 - f75113 4 gp34_ endb r/w 0 enable gpio34 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit4 . 3 gp33_ endb r/w 0 enable gpio33 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit3 . 2 gp32_ endb r/w 0 enable gpio32 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit2. 1 gp31_ endb r/w 0 enable gpio31 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit1 . 0 gp30_ endb r/w 0 enable gpio30 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 4ch bit0. 8.2.10 gpio3x pin inverse enable register ? index47h bit name r/w default description 7 gp37_ pinv r/w 0 if the gpio37 pin inverse was sele cted, the output signal would be inversed. 6 gp36_ pinv r/w 0 if the gpio36 pin inverse was sele cted, the output signal would be inversed. 5 gp35_ pinv r/w 0 if the gpio35 pin inverse was sele cted, the output signal would be inversed. 4 gp34_ pinv r/w 0 if the gpio34 pin inverse was sele cted, the output signal would be inversed. 3 gp33_ pinv r/w 0 if the gpio33 pin inverse was sele cted, the output signal would be inversed.
dec,2011 v0.13p - 58 - f75113 2 gp32_ pinv r/w 0 if the gpio32 pin inverse was sele cted, the output signal would be inversed. 1 gp31_ pinv r/w 0 if the gpio31 pin inverse was sele cted, the output signal would be inversed. 0 gp30_ pinv r/w 0 if the gpio30 pin inverse was sele cted, the output signal would be inversed. 8.2.11 gpio3x edge detector enable register ? index 48h bit name r/w default description 7 en_gp37edge r/w 0 enable gpio37 edge detector. if this bit set to 1 and gpio37 set to input mode (40h) will enable gpio37 edge detection. default is disabled. 6 en_gp36edge r/w 0 enable gpio36 edge detector. if this bit set to 1 and gpio36 set to input mode (40h) will enable gpio36 edge detection. default is disabled. 5 en_gp35edge r/w 0 enable gpio35 edge detector. if this bit set to 1 and gpio35 set to input mode (40h) will enable gpio35 edge detection. default is disabled. 4 en_gp34edge r/w 0 enable gpio34 edge detector. if this bit set to 1 and gpio34 set to input mode (40h) will enable gpio34 edge detection. default is disabled. 3 en_gp33edge r/w 0 enable gpio33 edge detector. if this bit set to 1 and gpio33 set to input mode (40h) will enable gpio33 edge detection. default is disabled. 2 en_gp32edge r/w 0 enable gpio32 edge detector. if this bit set to 1 and gpio32 set to input mode (40h) will enable gpio32 edge detection. default is disabled. 1 en_gp31edge r/w 0 enable gpio31 edge detector. if this bit set to 1 and gpio31 set to input mode (40h) will enable gpio31 edge detection. default is disabled. 0 en_gp30edge r/w 0 enable gpio30 edge detector. if this bit set to 1 and gpio30 set to input mode (40h) will enable gpio30 edge detection. default is disabled.
dec,2011 v0.13p - 59 - f75113 8.2.12 gpio3x edge detector status register ? index 49h bit name r/w default description 7 sts_gp37edge r - indicate gpio37 edge status. if set to 1, the edge of gpio37 has occurred. write 1 to clear this bit. writing 0 is invalid. 6 sts_gp36edge r - indicate gpio36 edge status. if set to 1, the edge of gpio36 has occurred. write 1 to clear this bit. writing 0 is invalid. 5 sts_gp35edge r - indicate gpio35 edge status. if set to 1, the edge of gpio35 has occurred. write 1 to clear this bit. writing 0 is invalid. 4 sts_gp34edge r - indicate gpio34 edge status. if set to 1, the edge of gpio34 has occurred. write 1 to clear this bit. writing 0 is invalid. 3 sts_gp33edge r - indicate gpio33 edge status. if set to 1, the edge of gpio33 has occurred. write 1 to clear this bit. writing 0 is invalid. 2 sts_gp32edge r - indicate gpio32 edge status. if set to 1, the edge of gpio32 has occurred. write 1 to clear this bit. writing 0 is invalid. 1 sts_gp31edge r - indicate gpio31 edge status. if set to 1, the edge of gpio31 has occurred. write 1 to clear this bit. writing 0 is invalid. 0 sts_gp30edge r - indicate gpio30 edge status. if set to 1, the edge of gpio30 has occurred. write 1 to clear this bit. writing 0 is invalid. 8.2.13 gpio3x smi enable register ? index 4ah bit name r/w default description 7 en_gp37smi r/w 0 enable gpio37 smi generation. if this bit set to 1, enable gpio37 to generate smi. 6 en_gp36smi r/w 0 enable gpio36 smi generation. if this bit set to 1, enable gpio36 to generate smi. 5 en_gp35smi r/w 0 enable gpio35 smi generation. if this bit set to 1, enable gpio35 to generate smi. 4 en_gp34smi r/w 0 enable gpio34 smi generation. if this bit set to 1, enable gpio34 to generate smi. 3 en_gp33smi r/w 0 enable gpio33 smi generation. if this bit set to 1, enable gpio33 to generate smi.
dec,2011 v0.13p - 60 - f75113 2 en_gp32smi r/w 0 enable gpio32 smi generation. if this bit set to 1, enable gpio32 to generate smi. 1 en_gp31smi r/w 0 enable gpio31 smi generation. if this bit set to 1, enable gpio31 to generate smi. 0 en_gp30smi r/w 0 enable gpio30 smi generation. if this bit set to 1, enable gpio30 to generate smi. 8.2.14 gpio3x output driving enable register ? index 4bh bit name r/w default description 7 en_gp37_obuf r/w 0 enable gpio37 drive high buffer. if this bit is set to 0, the pin gpio37 will be i/od pin, if set to 1 the pin gpio37 is i/o pin. 6 en_gp36_obuf r/w 0 enable gpio36 drive high buffer. if this bit is set to 0, the pin gpio36 will be i/od pin, if set to 1 the pin gpio36 is i/o pin. 5 en_gp35_obuf r/w 0 enable gpio35 drive high buffer. if this bit is set to 0, the pin gpio35 will be i/od pin, if set to 1 the pin gpio35 is i/o pin. 4 en_gp34_obuf r/w 0 enable gpio34 drive high buffer. if this bit is set to 0, the pin gpio34 will be i/od pin, if set to 1 the pin gpio34 is i/o pin. 3 en_gp33_obuf r/w 0 enable gpio33 drive high buffer. if this bit is set to 0, the pin gpio33 will be i/od pin, if set to 1 the pin gpio33 is i/o pin. 2 en_gp32_obuf r/w 0 enable gpio32 drive high buffer. if this bit is set to 0, the pin gpio32 will be i/od pin, if set to 1 the pin gpio32 is i/o pin. 1 en_gp31_obuf r/w 0 enable gpio31 drive high buffer. if this bit is set to 0, the pin gpio31 will be i/od pin, if set to 1 the pin gpio31 is i/o pin. 0 en_gp30_obuf r/w 0 enable gpio30 drive high buffer. if this bit is set to 0, the pin gpio30 will be i/od pin, if set to 1 the pin gpio30 is i/o pin. 8.2.15 gpio3x de-bounce time select register ? index 4ch bit name r/w default description 7 db_time37_sel r/w 0 select gpio37 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 6 db_time36_sel r/w 0 select gpio36 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 61 - f75113 5 db_time35_sel r/w 0 select gpio35 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 4 db_time34_sel r/w 0 select gpio34 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 3 db_time33_sel r/w 0 select gpio33 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 2 db_time32_sel r/w 0 select gpio32 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 1 db_time31_sel r/w 0 select gpio31 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 0 db_time30_sel r/w 0 select gpio30 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 8.2.16 gpio port edge status register ? index 50h bit name r/w default description 7-5 reserved - - reserved 4 sts_gp4eg r 0 indicate gpio4x edge status. if set to 1, the one edge of gpio4x port has occurred (reference index 79h). 3 sts_gp3eg r 0 indicate gpio3x edge status. if set to 1, the one edge of gpio3x port has occurred (reference index 49h). 2 sts_gp2eg r 0 indicate gpio2x edge status. if set to 1, the one edge of gpio2x port has occurred (reference index 39h). 1 sts_gp1eg r 0 indicate gpio1x edge status. if set to 1, the one edge of gpio1x port has occurred (reference index 29h). 0 sts_gp0eg r 0 indicate gpio0x edge status. if set to 1, the one edge of gpio0x port has occurred (reference index 19h). 8.2.17 sirq enable register ? index 51h bit name r/w default description 7-5 reserved - - reserved
dec,2011 v0.13p - 62 - f75113 4 serirq4_en r/w 0 1b: enable sirq function of gpio4x port. 0b: disable sirq function of gpio4x port. 3 serirq3_en r/w 0 1b: enable sirq function of gpio3x port. 0b: disable sirq function of gpio3x port. 2 serirq2_en r/w 0 1b: enable sirq function of gpio2x port. 0b: disable sirq function of gpio2x port. 1 serirq1_en r/w 0 1b: enable sirq function of gpio1x port. 0b: disable sirq function of gpio1x port. 0 serirq0_en r/w 0 1b: enable sirq function of gpio0x port. 0b: disable sirq function of gpio0x port. 8.2.18 sirq channel select0 register ? index 52h bit name r/w default description 7-4 sirqch_sel1 r/w 0 the register would select sirq channel of gpio1x port. 3-0 sirqch_sel0 r/w 0 the register would select sirq channel of gpio0x port. 8.2.19 sirq channel select1 register ? index 53h bit name r/w default description 7-4 sirqch_sel3 r/w 0 the register would select sirq channel of gpio3x port. 3-0 sirqch_sel2 r/w 0 the register would select sirq channel of gpio2x port. 8.2.20 sirq channel select2 register ? index 54h bit name r/w default description 7 sirq_actl_en r/w 0 0b: sirq function is active high. 1b: sirq function is active low. 6-4 reserved - - reserved 3-0 sirqch_sel4 r/w 0 the register would select sirq channel of gpio4x port.
dec,2011 v0.13p - 63 - f75113 8.2.21 access function internal pull-up enable register ? index 56h bit name r/w default description 7 reserved - - reserved 6 acs6_up_en r/w 0 enable internal pull-up in the lad3/gpio47 pin. 5 acs5_up_en r/w 0 enable internal pull-up in the lad2 pin. 4 acs4_up_en r/w 0 enable internal pull-up in the lad1 pin. 3 acs3_up_en r/w 0 enable internal pull-up in the lad0/spi_miso pin. 2 acs2_up_en r/w 0 enable internal pull-up in the lreset#/spi_mosi pin. 1 acs1_up_en r/w 0 enable internal pull-up in the lframe#/smbdat/spi_cs pin. 0 acs0_up_en r/w 0 enable internal pull- up in the lclk/smbclk/spi_clk pin. 8.2.22 wdt1 reset gpio function enable register ? index 57h bit name r/w default description 7 reserved - - reserved 6 reserved - - reserved 5 reserved - - reserved 4 wdt1_cgp4 _en r/w 0 set 1 to enable clear function of gpio4x register by wdt1 resetout. when watchdog timer1 count down to zero, the wdt1 resetout will clear gp_oct rl(70h), gp_odata(71h), gp_omode(73h), gp_plswd(74h), gp_reson(75h), gp_endb(76h), gp_plsin v(77h), en_gpedge(78h), sts_gpedge(79h), en_gpsmi( 7ah), en_gp_obuf(7bh), db_time_sel(7ch) register. 3 wdt1_cgp3_en r/w 0 set 1 to enable clear function of gpio3x register by wdt1 resetout. when watchdog timer1 count down to zero, the wdt1 resetout will clear gp_oct rl(40h), gp_odata(41h), gp_omode(43h), gp_plswd(44h), gp_reson(45h), gp_endb(46h), gp_plsin v(47h), en_gpedge(48h), sts_gpedge(49h), en_gpsmi( 4ah), en_gp_obuf(4bh), db_time_sel(4ch) register.
dec,2011 v0.13p - 64 - f75113 2 wdt1_cgp2_en r/w 0 set 1 to enable clear function of gpio2x register by wdt1 resetout. when watchdog timer1 count down to zero, the wdt1 resetout will clear gp_oct rl(30h), gp_odata(31h), gp_omode(33h), gp_plswd(34h), gp_reson(35h), gp_endb(36h), gp_plsin v(37h), en_gpedge(38h), sts_gpedge(39h), en_gpsmi( 3ah), en_gp_obuf(3bh), db_time_sel(3ch) register. 1 wdt1_cgp1_en r/w 0 set 1 to enable clear function of gpio1x register by wdt1 resetout. when watchdog timer1 count down to zero, the wdt1 resetout will clear gp_oct rl(20h), gp_odata(21h), gp_omode(23h), gp_plswd(24h), gp_reson(25h), gp_endb(26h), gp_plsin v(27h), en_gpedge(28h), sts_gpedge(29h), en_gpsmi( 2ah), en_gp_obuf(2bh), db_time_sel(2ch) register. 0 wdt1_cgp0_en r/w 0 set 1 to enable clear function of gpio0x register by wdt1 resetout. when watchdog timer1 count down to zero, the wdt1 resetout will clear gp_octrl(10h), gp_odata(11h), gp_omode(13h), gp_plswd(14h), gp_reson(15h), gp_endb(16h), gp_plsin v(17h), en_gpedge(18h), sts_gpedge(19h), en_gpsmi( 1ah), en_gp_obuf(1bh), db_time_sel(1ch) register. 8.2.23 wdt2 reset gpio function enable register ? index 58h bit name r/w default description 7 reserved - - reserved 6 reserved - - reserved 5 reserved - - reserved 4 wdt2_cgp4_en r/w 0 set 1 to enable clear function of gpio4x register by wdt2 resetout. when watchdog timer2 count down to zero, the wdt2 resetout will clear gp_oct rl(70h), gp_odata(71h), gp_omode(73h), gp_plswd(74h), gp_reson(75h), gp_endb(76h), gp_plsin v(77h), en_gpedge(78h), sts_gpedge(79h), en_gpsmi( 7ah), en_gp_obuf(7bh), db_time_sel(7ch) register.
dec,2011 v0.13p - 65 - f75113 3 wdt2_cgp3_en r/w 0 set 1 to enable clear function of gpio3x register by wdt2 resetout. when watchdog timer2 count down to zero, the wdt2 resetout will clear gp_oct rl(40h), gp_odata(41h), gp_omode(43h), gp_plswd(44h), gp_reson(45h), gp_endb(46h), gp_plsin v(47h), en_gpedge(48h), sts_gpedge(49h), en_gpsmi( 4ah), en_gp_obuf(4bh), db_time_sel(4ch) register. 2 wdt2_cgp2_en r/w 0 set 1 to enable clear function of gpio2x register by wdt2 resetout. when watchdog timer2 count down to zero, the wdt2 resetout will clear gp_oct rl(30h), gp_odata(31h), gp_omode(33h), gp_plswd(34h), gp_reson(35h), gp_endb(36h), gp_plsin v(37h), en_gpedge(38h), sts_gpedge(39h), en_gpsmi( 3ah), en_gp_obuf(3bh), db_time_sel(3ch) register. 1 wdt2_cgp1_en r/w 0 set 1 to enable clear function of gpio1x register by wdt2 resetout. when watchdog timer2 count down to zero, the wdt2 resetout will clear gp_oct rl(20h), gp_odata(21h), gp_omode(23h), gp_plswd(24h), gp_reson(25h), gp_endb(26h), gp_plsin v(27h), en_gpedge(28h), sts_gpedge(29h), en_gpsmi( 2ah), en_gp_obuf(2bh), db_time_sel(2ch) register. 0 wdt2_cgp0_en r/w 0 set 1 to enable clear function of gpio0x register by wdt2 resetout. when watchdog timer2 count down to zero, the wdt2 resetout will clear gp_octrl(10h), gp_odata(11h), gp_omode(13h), gp_plswd(14h), gp_reson(15h), gp_endb(16h), gp_plsin v(17h), en_gpedge(18h), sts_gpedge(19h), en_gpsmi( 1ah), en_gp_obuf(1bh), db_time_sel(1ch) register. 8.2.24 lreset reset gpio function enable register ? index 59h bit name r/w default description 7 reserved - - reserved 6 reserved - - reserved 5 reserved - - reserved
dec,2011 v0.13p - 66 - f75113 4 lrst_cgp4_en r/w 0 set 1 to enable clear function of gpio4x register by lreset. then lreset will clear gp_oct rl(70h), gp_o data(71h), gp_omode(73h), gp_plswd(74h), gp_reson(75h), gp_endb(76h), gp_plsin v(77h), en_gpedge(78h), sts_gpedge(79h), en_gpsmi( 7ah), en_gp_obuf(7bh), db_time_sel(7ch) register. 3 lrst_cgp3_en r/w 0 set 1 to enable gpio3x register clear function by lreset. then lreset will clear gp_oct rl(40h), gp_o data(41h), gp_omode(43h), gp_plswd(44h), gp_reson(45h), gp_endb(46h), gp_plsin v(47h), en_gpedge(48h), sts_gpedge(49h), en_gpsmi( 4ah), en_gp_obuf(4bh), db_time_sel(4ch) register. 2 lrst_cgp2_en r/w 0 set 1 to enable gpio2x register clear function by lreset. then lreset will clear gp_oct rl(30h), gp_o data(31h), gp_omode(33h), gp_plswd(34h), gp_reson(35h), gp_endb(36h), gp_plsin v(37h), en_gpedge(38h), sts_gpedge(39h), en_gpsmi( 3ah), en_gp_obuf(3bh), db_time_sel(3ch) register. 1 lrst_cgp1_en r/w 0 set 1 to enable gpio1x register clear function by lreset. then lreset will clear gp_oct rl(20h), gp_o data(21h), gp_omode(23h), gp_plswd(24h), gp_reson(25h), gp_endb(26h), gp_plsin v(27h), en_gpedge(28h), sts_gpedge(29h), en_gpsmi( 2ah), en_gp_obuf(2bh), db_time_sel(2ch) register. 0 lrst_cgp0_en r/w 0 set 1 to enable gpio0x register clear function by lreset. then lreset will clear gp_oct rl(10h), gp_odata(11h), gp_omode(13h), gp_plswd(14h), gp_reson(15h), gp_endb(16h), gp_plsin v(17h), en_gpedge(18h), sts_gpedge(19h), en_gpsmi( 1ah), en_gp_obuf(1bh), db_time_sel(1ch) register.
dec,2011 v0.13p - 67 - f75113 8.2.25 chip id1 register ? index 5ah bit name r/w default description 7-0 chip_id1 r 10h chip id1 8.2.26 chip id2 register ? index 5bh bit name r/w default description 7-0 chip_id2 r 11h chip id2 8.2.27 vender id1 register ? index 5dh bit name r/w default description 7-0 vender_id1 r 19h vender id1 8.2.28 vender id2 register ? index 5eh bit name r/w default description 7-0 vender_id2 r 34h vender id2 8.2.29 base address high byte register ? index 60h bit name r/w default description 7-0 ba_h r/w 00h the high-byte of base address 8.2.30 base address low byte register ? index 61h bit name r/w default description 7-0 ba_l r/w 00h the low-byte of base address if base-address was set to 0200h and users wrote dat a at index 0200h(0201h, 0202h, 0203h and 0204h), the gpio0x(gpio1x, gpio2x, gpio3x and gpio4x) would output the data that users wrot e. then, users read index 0200h(0201h, 0202h, 0203h or 0204h) and would got the stat us of gpio0x(gpio1x, gpio2x, gpio3x and gpio4x) pins. also, 0205h, 0206h and 0207h was reserved, so f751 13 would only compare bit 23 ~ bit 3 of base-address.
dec,2011 v0.13p - 68 - f75113 8.2.31 gpio4x output control register ? index 70h bit name r/w default description 7 gp47_octrl r/w 0 gpio47 output control. set to 1 for output function. set to 0 for input function (default). 6 gp46_octrl r/w 0 gpio46 output control. set to 1 for output function. set to 0 for input function (default). 5 gp45_octrl r/w 0 gpio45 output control. set to 1 for output function. set to 0 for input function (default). 4 gp44_octrl r/w 0 gpio44 output control. set to 1 for output function. set to 0 for input function (default). 3 gp43_octrl r/w 0 gpio43 output control. set to 1 for output function. set to 0 for input function (default). 2 gp42_octrl r/w 0 gpio42 output control. set to 1 for output function. set to 0 for input function (default). 1 gp41_octrl r/w 0 gpio41 output control. set to 1 for output function. set to 0 for input function (default). 0 gp40_octrl r/w 0 gpio40 output control. set to 1 for output function. set to 0 for input function (default). 8.2.32 gpio4x output data register ? index 71h bit name r/w default description 7 gp47_ odata r/w 0 gpio47 output data. 6 gp46_ odata r/w 0 gpio46 output data. 5 gp45_ odata r/w 0 gpio45 output data. 4 gp44_ odata r/w 0 gpio44 output data. 3 gp43_ odata r/w 0 gpio43 output data. 2 gp42_ odata r/w 0 gpio42 output data. 1 gp41_ odata r/w 0 gpio41 output data. 0 gp40_ odata r/w 0 gpio40 output data.
dec,2011 v0.13p - 69 - f75113 8.2.33 gpio4x input status register ? index 72h bit name r/w default description 7 gp47_ psts r - read the gpio47 data on the pin. 6 gp46_ psts r - read the gpio46 data on the pin. 5 gp45_ psts r - read the gpio45 data on the pin. 4 gp44_ psts r - read the gpio44 data on the pin. 3 gp43_ psts r - read the gpio43 data on the pin. 2 gp42_ psts r - read the gpio42 data on the pin. 1 gp41_ psts r - read the gpio41 data on the pin. 0 gp40_psts r - read the gpio40 data on the pin. 8.2.34 gpio4x level/pulse control register ? index 73h bit name r/w default description 7 gp47_ omode r/w 0 gpio47 output mode. 0 ? level, 1 ? pulse. 6 gp46_ omode r/w 0 gpio46 output mode. 0 ? level, 1 ? pulse. 5 gp45_ omode r/w 0 gpio45 output mode. 0 ? level, 1 ? pulse. 4 gp44_ omode r/w 0 gpio44 output mode. 0 ? level, 1 ? pulse. 3 gp43_ omode r/w 0 gpio43 output mode. 0 ? level, 1 ? pulse. 2 gp42_ omode r/w 0 gpio42 output mode. 0 ? level, 1 ? pulse. 1 gp41_ omode r/w 0 gpio41 output mode. 0 ? level, 1 ? pulse. 0 gp40_ omode r/w 0 gpio40 output mode. 0 ? level, 1 ? pulse. 8.2.35 gpio4x pulse width control register ? index 74h bit name r/w default description 7-2 reserved - - reserved 1-0 gp4_plswd r/w 0 gpio4x pulse width. if set the gpio4x to pulse mode, the pulse width can be defined as follows. 00b ? 500us (default) 01b ? 1ms 10b ? 20ms 11b ? 100ms
dec,2011 v0.13p - 70 - f75113 8.2.36 gpio4x pull-up resistor control register ? index 75h bit name r/w default description 7 gp47_ reson r/w 0 turn on the gpio47 pin internal pull-up resistor with 10k ? . 6 gp46_ reson r/w 0 turn on the gpio46 pin internal pull-up resistor with 10k ? . 5 gp45_ reson r/w 0 turn on the gpio45 pin internal pull-up resistor with 10k ? 4 gp44_ reson r/w 0 turn on the gpio44 pin internal pull-up resistor with 10k ? . 3 gp43_ reson r/w 0 turn on the gpio43 pin internal pull-up resistor with 10k ? . 2 gp42_ reson r/w 0 turn on the gpio42 pin internal pull-up resistor with 10k ? . 1 gp41_ reson r/w 0 turn on the gpio41 pin internal pull-up resistor with 10k ? . 0 gp40_ reson r/w 0 turn on the gpio40 pin internal pull-up resistor with 10k ? . 8.2.37 gpio4x input de-bounce register ? index 76h bit name r/w default description 7 gp47_ endb r/w 0 enable gpio47 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit7. 6 gp46_ endb r/w 0 enable gpio46 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit6 . 5 gp45_ endb r/w 0 enable gpio45 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit5 . 4 gp44_ endb r/w 0 enable gpio44 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit4. 3 gp43_ endb r/w 0 enable gpio43 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit3.
dec,2011 v0.13p - 71 - f75113 2 gp42_ endb r/w 0 enable gpio42 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit2. 1 gp41_ endb r/w 0 enable gpio41 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit1 . 0 gp40_ endb r/w 0 enable gpio40 input de-bounce with 10u (maximum, when input signal and detected clock is synchronicity) or 25ms (maximum, when input signal and detected clock is synchronicity) second that selected by 7ch bit0. 8.2.38 gpio4x pin inverse enable register ? index77h bit name r/w default description 7 gp47_ pinv r/w 0 if the gpio47 pin inverse was sele cted, the output signal would be inversed. 6 gp46_ pinv r/w 0 if the gpio46 pin inverse was sele cted, the output signal would be inversed. 5 gp45_ pinv r/w 0 if the gpio45 pin inverse was sele cted, the output signal would be inversed. 4 gp44_ pinv r/w 0 if the gpio44 pin inverse was sele cted, the output signal would be inversed. 3 gp43_ pinv r/w 0 if the gpio43 pin inverse was sele cted, the output signal would be inversed. 2 gp42_ pinv r/w 0 if the gpio42 pin inverse was sele cted, the output signal would be inversed. 1 gp41_ pinv r/w 0 if the gpio41 pin inverse was sele cted, the output signal would be inversed. 0 gp40_ pinv r/w 0 if the gpio40 pin inverse was sele cted, the output signal would be inversed.
dec,2011 v0.13p - 72 - f75113 8.2.39 gpio4x edge detector enable register ? index 78h bit name r/w default description 7 en_gp47edge r/w 0 enable gpio47 edge detector. if this bit set to 1 and gpio47 set to input mode (70h) will enable gpio47 edge detection. default is disabled. 6 en_gp46edge r/w 0 enable gpio46 edge detector. if this bit set to 1 and gpio46 set to input mode (70h) will enable gpio36 edge detection. default is disabled. 5 en_gp45edge r/w 0 enable gpio45 edge detector. if this bit set to 1 and gpio45 set to input mode (70h) will enable gpio35 edge detection. default is disabled. 4 en_gp44edge r/w 0 enable gpio44 edge detector. if this bit set to 1 and gpio44 set to input mode (70h) will enable gpio34 edge detection. default is disabled. 3 en_gp43edge r/w 0 enable gpio43 edge detector. if this bit set to 1 and gpio43 set to input mode (70h) will enable gpio33 edge detection. default is disabled. 2 en_gp42edge r/w 0 enable gpio42 edge detector. if this bit set to 1 and gpio42 set to input mode (70h) will enable gpio32 edge detection. default is disabled. 1 en_gp41edge r/w 0 enable gpio41 edge detector. if this bit set to 1 and gpio41 set to input mode (70h) will enable gpio31 edge detection. default is disabled. 0 en_gp40edge r/w 0 enable gpio40 edge detector. if this bit set to 1 and gpio40 set to input mode (70h) will enable gpio30 edge detection. default is disabled. 8.2.40 gpio4x edge detector status register ? index 79h bit name r/w default description 7 sts_gp47edge r - indicate gpio47 edge status. if set to 1, the edge of gpio47 has occurred. write 1 to clear this bit. writing 0 is invalid. 6 sts_gp46edge r - indicate gpio46 edge status. if set to 1, the edge of gpio46 has occurred. write 1 to clear this bit. writing 0 is invalid.
dec,2011 v0.13p - 73 - f75113 5 sts_gp45edge r - indicate gpio45 edge status. if set to 1, the edge of gpio45 has occurred. write 1 to clear this bit. writing 0 is invalid. 4 sts_gp44edge r - indicate gpio44 edge status. if set to 1, the edge of gpio44 has occurred. write 1 to clear this bit. writing 0 is invalid. 3 sts_gp43edge r - indicate gpio43 edge status. if set to 1, the edge of gpio43 has occurred. write 1 to clear this bit. writing 0 is invalid. 2 sts_gp42edge r - indicate gpio42 edge status. if set to 1, the edge of gpio42 has occurred. write 1 to clear this bit. writing 0 is invalid. 1 sts_gp41edge r - indicate gpio41 edge status. if set to 1, the edge of gpio41 has occurred. write 1 to clear this bit. writing 0 is invalid. 0 sts_gp40edge r - indicate gpio40 edge status. if set to 1, the edge of gpio40 has occurred. write 1 to clear this bit. writing 0 is invalid. 8.2.41 gpio4x smi enable register ? index 7ah bit name r/w default description 7 en_gp47smi r/w 0 enable gpio47 smi generation. if this bit set to 1, enable gpio47 to generate smi. 6 en_gp46smi r/w 0 enable gpio46 smi generation. if this bit set to 1, enable gpio46 to generate smi. 5 en_gp45smi r/w 0 enable gpio45 smi generation. if this bit set to 1, enable gpio45 to generate smi. 4 en_gp44smi r/w 0 enable gpio44 smi generation. if this bit set to 1, enable gpio44 to generate smi. 3 en_gp43smi r/w 0 enable gpio43 smi generation. if this bit set to 1, enable gpio43 to generate smi. 2 en_gp42smi r/w 0 enable gpio42 smi generation. if this bit set to 1, enable gpio42 to generate smi. 1 en_gp41smi r/w 0 enable gpio41 smi generation. if this bit set to 1, enable gpio41 to generate smi. 0 en_gp40smi r/w 0 enable gpio40 smi generation. if this bit set to 1, enable gpio40 to generate smi.
dec,2011 v0.13p - 74 - f75113 8.2.42 gpio4x output driving enable register ? index 7bh bit name r/w default description 7 en_gp47_obuf r/w 0 enable gpio47 drive high buffer. if this bit is set to 0, the pin gpio47 will be i/od pin, if set to 1 the pin gpio47 is i/o pin. 6 en_gp46_obuf r/w 0 enable gpio46 drive high buffer. if this bit is set to 0, the pin gpio46 will be i/od pin, if set to 1 the pin gpio46 is i/o pin. 5 en_gp45_obuf r/w 0 enable gpio45 drive high buffer. if this bit is set to 0, the pin gpio45 will be i/od pin, if set to 1 the pin gpio45 is i/o pin. 4 en_gp44_obuf r/w 0 enable gpio44 drive high buffer. if this bit is set to 0, the pin gpio44 will be i/od pin, if set to 1 the pin gpio44 is i/o pin. 3 en_gp43_obuf r/w 0 enable gpio43 drive high buffer. if this bit is set to 0, the pin gpio43 will be i/od pin, if set to 1 the pin gpio43 is i/o pin. 2 en_gp42_obuf r/w 0 enable gpio42 drive high buffer. if this bit is set to 0, the pin gpio42 will be i/od pin, if set to 1 the pin gpio42 is i/o pin. 1 en_gp41_obuf r/w 0 enable gpio41 drive high buffer. if this bit is set to 0, the pin gpio41 will be i/od pin, if set to 1 the pin gpio41 is i/o pin. 0 en_gp40_obuf r/w 0 enable gpio40 drive high buffer. if this bit is set to 0, the pin gpio40 will be i/od pin, if set to 1 the pin gpio40 is i/o pin. 8.2.43 gpio4x de-bounce time select register ? index 7ch bit name r/w default description 7 db_time47_sel r/w 0 select gpio47 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 6 db_time46_sel r/w 0 select gpio46 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 5 db_time45_sel r/w 0 select gpio45 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 4 db_time44_sel r/w 0 select gpio44 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 3 db_time43_sel r/w 0 select gpio43 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 75 - f75113 2 db_time42_sel r/w 0 select gpio42 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 1 db_time41_sel r/w 0 select gpio41 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default). 0 db_time40_sel r/w 0 select gpio40 input de-bounce time. if set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 10us (default).
dec,2011 v0.13p - 76 - f75113 9. electrical characteristic absolute maximum ratings parameter rating unit power supply voltage -0.5 to 4.0 v input voltage -0.5 to 5.5 v operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under abso lute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) (note) parameter conditons min typ max unit temperature error, remote diode 60 o c < t d < 145 o c, vcc = 3.0v to 3.6v 0 o c dec,2011 v0.13p - 77 - f75113 i/ood 16st5v - ttl level bi-directional pin, output pin with 16ma source-sink capability, schmitt trigger, 5v tolerance and can programming to open-drain function. input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol -16 -9 ma vol = 0.4 v output high current ioh +9 +16 ma voh = 2.4v input high leakage ilih +1 in st5v - ttl level input pin with schmitt trigger, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 in l v - low level input input low voltage vil 0.3 v input high voltage vih 0.9 v input high leakage ilih +1 a vin = 1.2v input low leakage ilil -1 a vin = 0 v od 16st5v - open-drain output with16 ma sink capab ility, schmitt trigger, 5v tolerance. output low current iol -16 ma vol = 0.4v ac characteristics 9.3.1 lpc interface no. description min. max. unit t1 lframe# drive low after rising edge of lclk 2 12 ns t2 lframe# drive high after rising edge of lclk 2 12 ns t3 lda[3:0] floating after rising edge of lclk 28 ns t4 lda[3:0] setup time to rising edge of lclk 7 ns t5 lda[3:0] hold time from rising edge of lclk 0 ns t6 period of lclk 27 33 ns t7 duration of lclk low 12 ns t8 duration of lclk high 12 ns lpc interface timing table
dec,2011 v0.13p - 78 - f75113 typical timing for host read lclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t1 t2 t4 t5 t3 0110 0 - i clocks 4 or 8 clocks 2 - 2k clocks 1 - j clocks host read timing diagram typical timing for host write lclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t6 t7 t8 host write timing diagram timing for aboart mechanism lclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync 0110 0 - i clocks 4 or 8 clocks too many syncs causes timeout sync peripheral must stop driving host will drive high host abort timing diagram
dec,2011 v0.13p - 79 - f75113 9.3.2 serialized irq interface no. description min. max. unit t1 host drive serirq low after rising edge of pciclk 2 12 ns t2 host drive serirq high after rising edge of pciclk 2 12 ns t3 slave drive serirq low after rising edge of pciclk 2 12 ns t4 slave drive serirq high after rising edge of pciclk 2 12 ns t5 period of pciclk 27 33 ns t6 duration of pciclk low 12 ns t7 duration of pciclk high 12 ns sirq interface timing table start frame timing pciclk serirq drive source t1 t2 4 - 8 clocks start h sl or h r t start frame irq0 frame r t s irq1 frame r t s irq2 frame r t s irq1 host controller none irq1 none h : host control sl : slave control r : recovery t : turn-around s : sample t3 t4 sirq start frame timing diagram stop frame timing pciclk serirq drive source t1 t2 2 or 3 clocks stop hr t stop frame irq14 frame r t s irq15 frame r t s iochck# frame r t s host controller none irq15 h : host control sl : slave control r : recovery t : turn-around s : sample i : idle i next cycl e none 0 - n clocks t5 t6 t7 sirq stop frame timing diagram
dec,2011 v0.13p - 80 - f75113 9.3.3 smbus interface valid data scl sda in sda out t hd;sda t scl t hd;dat t su;sto t su;dat serial bus timing diagram t r t r serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns 9.3.4 spi interfcae /cs clk hmosi tchsl msb in tslch tdvch tchdx lsb in tshsl tshch tchsh tclch tchcl hmiso high impedance spi timing diagram
dec,2011 v0.13p - 81 - f75113 spi timing parameter symbol min. max. unit /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch 2 ns /cs active setup time relative to clk t slch 5 ns data in hold time t chdx 5 ns clock rise time peak to peak t clch 0.1 v/ns /cs active hold time relative to clk t chsh 10 ns /cs deselect time t shsl 100 ns /cs not active setup time relative to clk t shch 0 ns clock fall time peak to peak t chcl 0.1 v/ns 9.3.5 internal clock description min. max. unit internal clock 400 600 khz
dec,2011 v0.13p - 82 - f75113 10. ordering information part number package type production flow F75113U 48 pin tqfp commercial, 0 c to +70 c 11. top marking specification the version identification is shown as the bold red three characters. please refer to below table for detail: F75113U xxxxxx x xxxxxx.x fintek logo 1 st line: device name ? F75113U, where u means the package code 2 nd line: assembly plant code (x) + assembled year code (x) + week code (xx) + fintek internal code (xx) + ic version (x) where a means version a, b means version b, ? 3 rd line: wafer fab code (fxxx?xx) : pin 1 identifier fintek
dec,2011 v0.13p - 83 - f75113 12. package dimensions 48tqfp (7mm x 7mm)
dec,2011 v0.13p - 84 - f75113 symbols min. nom. max. a - - 1.20 a1 0.05 - 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 - 0.16 d 9.00 bsc d1 7.00 bsc e 9.00 bsc e1 7.00 bsc e 0.50 bsc l 0.45 0.60 0.75 l1 1.00 ref 0 0 3.5 0 7 0 unit: mm pad size e2 d2 min. max. min. max. 160x160 mil2 3.05 4.06 3.05 4.06 unit: mm feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owner
- 85 - dec , 2011 v0.13p 13. application circuits tit le size document number rev date: sheet of 1.1 f75113 application circuit b 11 friday , july 08, 2011 lpc_rst#/spi_mosi led13 d1 led r3 330 led10 led11 led12 led14 led15 led16 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 r1 10k led17 vcc3v lpc_lad0/spi_miso lclk/smbclk/spi_clk lpc_rst#/spi_mosi lpc_lad0/spi_miso lframe#/smbdat/spi_cs# 1 2 3 4 j2 con4 lclk/smbclk/spi_clk lframe#/smbdat/spi_cs# lclk/smbclk/spi_clk r56 0r r57 0r r58 0r r59 0r r60 0r r61 0r r62 0r lclk lframe# lreset# lad1 lad0 lad3 lad2 lpc_lad1 vcc3v lpc_lad2 lpc_lad1 l p c i n t e r f a c e smbclk lpc_lad3 smbdat r46 10k 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 r2 10k s m b u s i n t e r f a c e r47 10k r63 10k r64 10k lpc_lad2 lpc_lad3 r65 10k w h e n u s i n g s m b u s i n t e r f a c e : 1 . l p c i n t e r f a c e p i n s m u s t b e p u l l h i g h . 2 . l p c s i g n a l s a r e n o t a l l o w e d t o c o n n e c t e d t o f 7 5 1 1 3 gpio40 r66 10k r67 10k vcc3v lframe#/smbdat/spi_cs# lpc_rst#/spi_mosi lpc_rst#/spi_mosi lpc_lad0/spi_miso lpc_lad1 r68 10k s p i i n t e r f a c e vcc3v r69 10k r70 10k lpc_lad3 lpc_lad2 w h e n u s i n g s p i i n t e r f a c e : 1 . l p c i n t e r f a c e p i n s m u s t b e p u l l h i g h . 2 . l p c s i g n a l s a r e n o t a l l o w e d t o c o n n e c t e d t o f 7 5 1 1 3 vcc3v gpio05 gpio06 gpio07 gpio34 gpio35 gpio36 gpio37 gpio04 vcc3v lad0/spi_miso 1 lad1 2 lad2 3 lad3/gpio47 4 gpio46 5 gpio45 6 gpio44 7 vdd 8 gpio27/led27 9 gpio26/led26 10 gpio25/led25 11 gpio24/led24 12 gpio23/led23 13 gpio22/led22 14 gpio21/led21 15 gpio20/led20 16 gpio37 17 gpio36 18 gpio35 19 gpio34 20 pgio07/led07/smi/rstout2 21 pgio06/led06/smi/rstout2 22 pgio05/led05/smi/rstout2 23 gpio03/led03/smi/rstout1 25 gpio02/led02/smi/rstout1 26 gpio01/led01/smi/rstout1 27 gpio00/led00/smi/rstout1 28 gpio33 29 gpio32 30 gpio31 31 gpio30 32 gpio17/led17/touch7 33 gpio16/led16/touch6 34 gpio15/led15/touch5 35 gpio14/led14/touch4 36 gpio13/led13/touch3 37 gpio12/led12/touch2 38 gpio11/led11/touch1 39 gpio10/led10/touch0 40 vss 41 gpio43 42 gpio42 43 gpio41 44 gpio40 45 lclk/smbclk/spi_clk 46 lframe#/smbdat/spi_cs# 47 lreset#/spi_mosi 48 pgio04/led04/smi/rstout2 24 u5 F75113U gpio22 gpio23 gpio24 gpio25 gpio26 gpio27 gpio20 gpio21 lpc_lad0/spi_miso r12 10k r13 10k r14 10k gpio44 gpio45 gpio46 vcc3v c1 0.1uf 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 r11 10k r15 10k r16 10k gpio32 gpio31 gpio30 gpio03 gpio02 gpio01 gpio00 gpio33 r17 10k gpio43 gpio42 lframe#/smbdat/spi_cs# gpio41 r18 10k vcc3v lclk/smbclk/spi_clk r4 330 d2 led d3 led r5 330 r6 330 d4 led d5 led r7 330 r8 330 d6 led d7 led r9 330 r10 330 d8 led lpc_lad3 lpc_lad2 lpc_lad1

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